Match the following : Codes :List - I List - II (a) TTL (i) Consumer maximum power (b) ECL (ii) Highest Packaging Density (c) NMOS (iii) Least power consumption (d) CMOS (iv) Saturated logic
(a)-(iv), (b)-(i), (c)-(ii), (d)-(iii)
Each phrase names the one property that distinguishes its family.
(a) TTL → (iv) saturated logic. In a standard TTL gate the output transistor is driven hard into saturation for a logic LOW, with VCE(sat) around 0.2 V. That is what makes the levels robust, but saturation stores excess charge in the base, and sweeping it out again is what limits the switching speed. Schottky TTL solves this by clamping the collector-base junction with a Schottky diode so the transistor never quite saturates.
(b) ECL → (i) consumes maximum power. Emitter-coupled logic is the opposite design philosophy: a differential pair steered by a current source, whose transistors are never allowed to saturate. That makes it the fastest bipolar family — propagation delays of about 1 ns — but the current source runs continuously whatever the logic state, so ECL dissipates far more than any other family, typically 25 mW per gate.
(c) NMOS → (ii) highest packaging density. An NMOS gate needs only one transistor per input plus a single load device, whereas CMOS needs a matched pair for every input. For the same silicon area an NMOS process therefore fits substantially more gates, which is why the early microprocessors were NMOS.
(d) CMOS → (iii) least power consumption. In either steady state one of the complementary transistors is off, so no DC path exists between supply and ground and the static current is only leakage. Power is consumed essentially only while switching:
\(P=C_{L}V_{DD}^{2}f\)
| Family | Signature | Speed | Power/gate |
|---|---|---|---|
| TTL | Saturated logic | 10 ns | 10 mW |
| ECL | Non-saturated, current steering | 1 ns | 25 mW |
| NMOS | Highest density | Moderate | Moderate |
| CMOS | Complementary pair | Moderate | μW static |
The order (iv), (i), (ii), (iii) is option 3.
The lasting consequence is visible in the formula above: CMOS power grows with frequency, so as clock rates climbed the "free" static power advantage narrowed — which is why modern design pushes supply voltage down, since the dependence on VDD is quadratic.
Hence, the correct match is (a)-(iv), (b)-(i), (c)-(ii), (d)-(iii).
Similar Questions
Arrange in ascending order based on power dissipation the following logic families :
(i) ECL
(ii) TTL
(iii) CMOSMatch the following :
List – I List – II a. I2L i. XOR b. high impedance state ii. non-saturation logic c. controlled inverter iii. tristate d. ECL iv. bipolar logic Codes :
Given that for a logic family :
(A) VOH is the maximum output high level voltage
(B) VOL is the maximum input low level voltage
(C) VIH is the minimum input acceptable input high voltage level
(D) VIL is the minimum acceptable input low voltage levelChoose the most appropriate answer from the options given below :
The logic families have fan out more than TTL
A. RTL
B. ECL
C. DTL
D. CMOS
Choose the correct answer from the options given below.
Match the following lists in terms of power dissipation/Gate:
List – I List – II a. BiCMOS i. 6 mW b. ECL ii. 2.75 μW c. CMOS (AHC) iii. 25 mW to 73 mW d. bipolar TTL (F) iv. 17 μw Choose the correct answer from the codes given below:
Arrange the following in terms of decreasing order of power dissipation :
(a) CMOS
(b) ECL
(c) TTL
(d) MOS
The correct sequence of decreasing order of power dissipation is
For a three state TTL following statements are given :
(a) It allows to connect outputs directly.
(b) It allows to connect the inputs directly.
(c) It is used to decrease the switching time.
(d) It is used to increase the switching time in order to interface the peripherals for matching the speed with computer.
Which of the above are correct ?
Match the following in context of Fan out of various families :
List - I List - II (a) DTL (i) 20 (b) TTL (ii) 30 (c) PMOS (iii) 50 (d) CMOS (iv) 5 to 15 Codes :
For wired AND connection we should use :
Match the following lists :
List – I List – II a. IC 7400 i. Quad 2-input NOR gate b. IC 7402 ii. Quad 2-input AND gate c. IC 7408 iii. Quad 2-input OR gate d. IC 7432 iv. Quad 2-input NAND gate
Important Questions from Logic Families
Which of the following pair is correct?
I. RTL – Saturated bipolar logic family
II. ECL – Non-Saturated bipolar logic family
- Which of the following logic families has the maximum noise margin?
The figure of merit of digital IC is defined as:
- Which of the following logic families has the highest packing density?
The figure of merit of logic family is often measured in the unit of:
