CMOS dissipates least, ECL most, so ascending order is CMOS, TTL, ECL — (iii), (ii), (i), option 2.

Why CMOS dissipates almost nothing when idle. Every gate is a complementary pair, and in either stable state exactly one of the two transistors is off. No DC path exists from supply to ground, so the only static current is leakage. Power is consumed only while switching, in charging the load capacitance:

\(P=fCV^{2}\)

which makes dissipation proportional to clock frequency — a CMOS chip run fast enough will eventually dissipate as much as a bipolar one, but a static CMOS memory holds its data on microwatts.

Why TTL sits in the middle. Its totem-pole output and multi-emitter input draw current continuously through the internal resistors whatever the state, so power is dissipated even when nothing changes. It is roughly constant with frequency, unlike CMOS.

Why ECL is the worst — and why that is deliberate. ECL is a differential pair biased so that it never saturates. The transistors are steered between two states while both remain in the active region, so the tail current flows continuously. Avoiding saturation removes the stored-charge delay that slows TTL, giving sub-nanosecond switching — the fastest of the three by a wide margin.

The pattern to carry away is that speed and power trade against each other directly in this list: the order for propagation delay is exactly the reverse of the order for dissipation. ECL bought its speed with current; CMOS bought its low power with slower switching, at least until scaling made it fast as well — which is why CMOS eventually displaced both, and why ECL survives only in specialist high-speed roles.

Hence, the ascending order of power dissipation is (iii), (ii), (i).