Match the following in context of Fan out of various families : Codes :List - I List - II (a) DTL (i) 20 (b) TTL (ii) 30 (c) PMOS (iii) 50 (d) CMOS (iv) 5 to 15
a-(iv), b-(ii), c-(i), d-(iii)
a-(iv), b-(ii), c-(i), d-(iii) — option 2. DTL = 5 to 15, TTL = 30, PMOS = 20, CMOS = 50.
What fan-out measures. The number of similar gate inputs one output can drive while still holding valid logic levels:
\(\text{Fan-out}=\min\left(\dfrac{I_{OL}}{I_{IL}},\ \dfrac{I_{OH}}{I_{IH}}\right)\)
So it is decided by how much input current each load demands — which is why the MOS families, whose inputs are insulated gates drawing no DC current at all, sit far above the bipolar ones.
The two MOS entries are certain, and they anchor the whole matching.
| Pairing | Why it is fixed |
|---|---|
| d → (iii), CMOS = 50 | The largest figure in the list must belong to CMOS. Its input is a capacitor, not a current sink, so the DC limit is effectively infinite and the quoted 50 is a practical bound set by accumulated capacitance slowing the edges, not by loading |
| c → (i), PMOS = 20 | The other MOS family, likewise drawing no DC input current, takes the next highest value. 20 is the standard figure quoted for MOS logic |
The two bipolar families then take what is left — 5 to 15, and 30 — and the order between them follows from which family loads its driver harder.
| DTL | TTL | |
|---|---|---|
| Input stage | Diode input; each load draws appreciable current from the driving stage through the input diode | Multi-emitter transistor input, which presents a lighter load in the low state |
| Fan-out | Lower — item (iv), 5 to 15, with the usual quoted value around 8 | Higher — item (ii), 30 |
So a → (iv) and b → (ii). The point to carry away is the ordering: DTL sits below TTL, and both sit below the MOS families. Reversing DTL and TTL is the single error this item is built to catch, and it yields option 4 — the distractor.
The resulting table.
| Family | Input type | Fan-out |
|---|---|---|
| DTL | diode input, bipolar | 5 to 15 |
| TTL | multi-emitter bipolar | 30 |
| PMOS | insulated gate | 20 |
| CMOS | insulated gate | 50 |
Why fan-out matters in design. Exceeding it does not merely slow the circuit — the output voltage drifts out of the valid band, the noise margin collapses and the logic becomes unreliable. Where more loads are needed a buffer or line driver is inserted, and in MOS designs the real limit is timing: each extra input adds capacitance and lengthens the RC transition.
Hence, the matching is a-(iv), b-(ii), c-(i), d-(iii).
Similar Questions
Arrange in ascending order based on power dissipation the following logic families :
(i) ECL
(ii) TTL
(iii) CMOSMatch the following :
List – I List – II a. I2L i. XOR b. high impedance state ii. non-saturation logic c. controlled inverter iii. tristate d. ECL iv. bipolar logic Codes :
Given that for a logic family :
(A) VOH is the maximum output high level voltage
(B) VOL is the maximum input low level voltage
(C) VIH is the minimum input acceptable input high voltage level
(D) VIL is the minimum acceptable input low voltage levelChoose the most appropriate answer from the options given below :
The logic families have fan out more than TTL
A. RTL
B. ECL
C. DTL
D. CMOS
Choose the correct answer from the options given below.
Match the following lists in terms of power dissipation/Gate:
List – I List – II a. BiCMOS i. 6 mW b. ECL ii. 2.75 μW c. CMOS (AHC) iii. 25 mW to 73 mW d. bipolar TTL (F) iv. 17 μw Choose the correct answer from the codes given below:
Arrange the following in terms of decreasing order of power dissipation :
(a) CMOS
(b) ECL
(c) TTL
(d) MOS
The correct sequence of decreasing order of power dissipation is
For a three state TTL following statements are given :
(a) It allows to connect outputs directly.
(b) It allows to connect the inputs directly.
(c) It is used to decrease the switching time.
(d) It is used to increase the switching time in order to interface the peripherals for matching the speed with computer.
Which of the above are correct ?
For wired AND connection we should use :
Match the following :
List - I List - II (a) TTL (i) Consumer maximum power (b) ECL (ii) Highest Packaging Density (c) NMOS (iii) Least power consumption (d) CMOS (iv) Saturated logic Codes :
Match the following lists :
List – I List – II a. IC 7400 i. Quad 2-input NOR gate b. IC 7402 ii. Quad 2-input AND gate c. IC 7408 iii. Quad 2-input OR gate d. IC 7432 iv. Quad 2-input NAND gate
Important Questions from Logic Families
Which of the following pair is correct?
I. RTL – Saturated bipolar logic family
II. ECL – Non-Saturated bipolar logic family
- Which of the following logic families has the maximum noise margin?
The figure of merit of digital IC is defined as:
- Which of the following logic families has the highest packing density?
The figure of merit of logic family is often measured in the unit of:
