Rank by how each family draws current.

(b) ECL — highest, about 25–60 mW per gate. Emitter-coupled logic keeps a differential pair permanently biased and never lets its transistors saturate. That standing current is what gives ECL the shortest propagation delay of any bipolar family, and it is drawn whether the gate is switching or not.

(c) TTL — next, about 2–10 mW per gate. Current flows whenever the output transistors conduct, so dissipation is substantial but an order of magnitude below ECL.

(d) MOS — lower still. Single-channel NMOS or PMOS logic uses a resistive or depletion-mode load, so a d.c. path exists between supply and ground whenever the output is low — giving static dissipation in the microwatt-to-milliwatt range, well below the bipolar families but not zero.

(a) CMOS — lowest, microwatts static. The complementary pair guarantees that one transistor is always off, so in either steady state there is no conducting path from V_DD to ground and only leakage flows. Its power is essentially dynamic:

\(P=\alpha C_LV_{DD}^{2}f\)

which is why CMOS dissipation rises with clock frequency and why supply voltages have been scaled down so aggressively — the V² term dominates.

Decreasing order:

\(ECL \gt TTL \gt MOS \gt CMOS \Rightarrow (b),\,(c),\,(d),\,(a)\)

The pattern to carry away: bipolar families burn steady bias current and are fast; MOS families avoid it and are slower but denser; and CMOS eliminates static current altogether, which is precisely why it displaced everything else once switching speeds became adequate.

Hence, the decreasing order of power dissipation is (b), (c), (d), (a).