For wired AND connection we should use :
TTL gates without active pull up and with open collector
TTL gates without active pull up and with open collector — option 3.
Why wired-AND needs open-collector outputs. A wired-AND (also called wired logic or a dot-AND) is made by tying several gate outputs to one node and adding a single external pull-up resistor to \(V_{CC}\). The node then sits HIGH only when every output is off, and any one gate pulling LOW drags the whole node down — which is the AND function, obtained from wiring alone with no gate at all.
That works only if a gate can release the node entirely. An open-collector output can: its output transistor either sinks current to ground or is simply open.
Why a totem-pole (active pull-up) output must not be wired. The standard TTL output stage has an active pull-up — a transistor that actively drives the node HIGH. Tie two such outputs together with one HIGH and one LOW and you create a low-impedance path straight from \(V_{CC}\) to ground through the two output transistors :
| Consequence | Effect |
|---|---|
| Large current spike | Tens of milliamps, limited only by the saturation resistances |
| Indeterminate output level | The node settles somewhere between the two valid bands, so the logic level is invalid |
| Device damage | Sustained conduction overheats and can destroy the output stage |
Why option 3 rather than option 2. Both name the open collector, and on that point both are right; option 3 is the fuller and more precise statement, because it says explicitly what must be absent — the active pull-up — as well as what must be present. Since the defect that makes ordinary TTL unusable here is precisely the active pull-up, the option that rules it out in terms is the better answer, and it is the one the key records. Option 4, “any of the above”, is wrong for the same reason: it would admit the active pull-up gate of option 1.
The cost of wired-AND, since it is not free: the external pull-up resistor is a passive load, so the LOW-to-HIGH transition is a slow RC charge rather than an actively driven edge. The value of that resistor is a compromise — small enough for acceptable speed and noise margin, large enough that the sinking gate is not overloaded in the LOW state.
The modern equivalent is the open-drain output in CMOS, used for exactly the same reasons on shared buses such as I²C, where many devices must be able to pull a common line low. Tri-state outputs are a different device: they can be turned off too, but only one may drive the bus at a time, so they are for bus sharing, not for forming logic.
Hence, the answer is TTL gates without active pull up and with open collector.
Similar Questions
Arrange in ascending order based on power dissipation the following logic families :
(i) ECL
(ii) TTL
(iii) CMOSMatch the following :
List – I List – II a. I2L i. XOR b. high impedance state ii. non-saturation logic c. controlled inverter iii. tristate d. ECL iv. bipolar logic Codes :
Given that for a logic family :
(A) VOH is the maximum output high level voltage
(B) VOL is the maximum input low level voltage
(C) VIH is the minimum input acceptable input high voltage level
(D) VIL is the minimum acceptable input low voltage levelChoose the most appropriate answer from the options given below :
The logic families have fan out more than TTL
A. RTL
B. ECL
C. DTL
D. CMOS
Choose the correct answer from the options given below.
Match the following lists in terms of power dissipation/Gate:
List – I List – II a. BiCMOS i. 6 mW b. ECL ii. 2.75 μW c. CMOS (AHC) iii. 25 mW to 73 mW d. bipolar TTL (F) iv. 17 μw Choose the correct answer from the codes given below:
Arrange the following in terms of decreasing order of power dissipation :
(a) CMOS
(b) ECL
(c) TTL
(d) MOS
The correct sequence of decreasing order of power dissipation is
For a three state TTL following statements are given :
(a) It allows to connect outputs directly.
(b) It allows to connect the inputs directly.
(c) It is used to decrease the switching time.
(d) It is used to increase the switching time in order to interface the peripherals for matching the speed with computer.
Which of the above are correct ?
Match the following in context of Fan out of various families :
List - I List - II (a) DTL (i) 20 (b) TTL (ii) 30 (c) PMOS (iii) 50 (d) CMOS (iv) 5 to 15 Codes :
Match the following :
List - I List - II (a) TTL (i) Consumer maximum power (b) ECL (ii) Highest Packaging Density (c) NMOS (iii) Least power consumption (d) CMOS (iv) Saturated logic Codes :
Match the following lists :
List – I List – II a. IC 7400 i. Quad 2-input NOR gate b. IC 7402 ii. Quad 2-input AND gate c. IC 7408 iii. Quad 2-input OR gate d. IC 7432 iv. Quad 2-input NAND gate
Important Questions from Logic Families
Which of the following pair is correct?
I. RTL – Saturated bipolar logic family
II. ECL – Non-Saturated bipolar logic family
- Which of the following logic families has the maximum noise margin?
The figure of merit of digital IC is defined as:
- Which of the following logic families has the highest packing density?
The figure of merit of logic family is often measured in the unit of:
