Given that for a logic family : (A) VOH is the maximum output high level voltage Choose the most appropriate answer from the options given below :
(B) VOL is the maximum input low level voltage
(C) VIH is the minimum input acceptable input high voltage level
(D) VIL is the minimum acceptable input low voltage level
(A), (C), (D), (B)
The four levels have a fixed order on the voltage axis, and listing them from highest to lowest gives VOH, VIH, VIL, VOL — that is (A), (C), (D), (B), option 2.
\(V_{OH}\gt V_{IH}\gt V_{IL}\gt V_{OL}\)
Why that ordering is forced, and not merely conventional. Take the two ends first. \(V_{OH}\) is what a driving gate guarantees to produce for a logic 1, and \(V_{IH}\) is the least a receiving gate will accept as a 1. For the two gates to work together at all, the driver must produce more than the receiver demands:
\(V_{OH}\gt V_{IH}\)
and the surplus is the high-level noise margin. Symmetrically at the bottom, \(V_{OL}\) is the highest voltage the driver produces for a 0, and \(V_{IL}\) the highest the receiver still reads as 0, so
\(V_{IL}\gt V_{OL}\)
with that surplus being the low-level margin. In the middle, \(V_{IH}\gt V_{IL}\) simply because the two input thresholds bracket the forbidden region where the gate's behaviour is undefined.
| Level | Belongs to | Meaning |
|---|---|---|
| VOH | Output | Minimum guaranteed high — highest of the four |
| VIH | Input | Minimum accepted as high |
| VIL | Input | Maximum accepted as low |
| VOL | Output | Maximum guaranteed low — lowest of the four |
A caution on the printed wording. Two of the descriptions are loosely phrased: \(V_{OL}\) is an output level, not an input one as (B) says, and \(V_{IL}\) is the maximum voltage still read as low rather than the minimum as (D) says. Neither slip affects the ordering, which is what the question is testing, and the letters still fall in the sequence above.
Typical figures for 5 V TTL make the ladder concrete: \(V_{OH}=2.7\) V, \(V_{IH}=2.0\) V, \(V_{IL}=0.8\) V, \(V_{OL}=0.5\) V — giving noise margins of 0.7 V high and 0.3 V low, and a forbidden band of 1.2 V between the two input thresholds.
Hence, the order is (A), (C), (D), (B).
Similar Questions
Arrange in ascending order based on power dissipation the following logic families :
(i) ECL
(ii) TTL
(iii) CMOSMatch the following :
List – I List – II a. I2L i. XOR b. high impedance state ii. non-saturation logic c. controlled inverter iii. tristate d. ECL iv. bipolar logic Codes :
The logic families have fan out more than TTL
A. RTL
B. ECL
C. DTL
D. CMOS
Choose the correct answer from the options given below.
Match the following lists in terms of power dissipation/Gate:
List – I List – II a. BiCMOS i. 6 mW b. ECL ii. 2.75 μW c. CMOS (AHC) iii. 25 mW to 73 mW d. bipolar TTL (F) iv. 17 μw Choose the correct answer from the codes given below:
Arrange the following in terms of decreasing order of power dissipation :
(a) CMOS
(b) ECL
(c) TTL
(d) MOS
The correct sequence of decreasing order of power dissipation is
For a three state TTL following statements are given :
(a) It allows to connect outputs directly.
(b) It allows to connect the inputs directly.
(c) It is used to decrease the switching time.
(d) It is used to increase the switching time in order to interface the peripherals for matching the speed with computer.
Which of the above are correct ?
Match the following in context of Fan out of various families :
List - I List - II (a) DTL (i) 20 (b) TTL (ii) 30 (c) PMOS (iii) 50 (d) CMOS (iv) 5 to 15 Codes :
For wired AND connection we should use :
Match the following :
List - I List - II (a) TTL (i) Consumer maximum power (b) ECL (ii) Highest Packaging Density (c) NMOS (iii) Least power consumption (d) CMOS (iv) Saturated logic Codes :
Match the following lists :
List – I List – II a. IC 7400 i. Quad 2-input NOR gate b. IC 7402 ii. Quad 2-input AND gate c. IC 7408 iii. Quad 2-input OR gate d. IC 7432 iv. Quad 2-input NAND gate
Important Questions from Logic Families
Which of the following pair is correct?
I. RTL – Saturated bipolar logic family
II. ECL – Non-Saturated bipolar logic family
- Which of the following logic families has the maximum noise margin?
The figure of merit of digital IC is defined as:
- Which of the following logic families has the highest packing density?
The figure of merit of logic family is often measured in the unit of:
