Match the following : Codes :List – I List – II a. I2L i. XOR b. high impedance state ii. non-saturation logic c. controlled inverter iii. tristate d. ECL iv. bipolar logic
a-iv, b-iii, c-i, d-ii
Two of the pairings are near-definitions — high impedance state means tristate, and ECL means non-saturating — and they leave only one consistent code: a-iv, b-iii, c-i, d-ii, option 4.
| Item | Match |
|---|---|
| a. I2L | iv. Bipolar logic |
| b. High impedance state | iii. Tristate |
| c. Controlled inverter | i. XOR |
| d. ECL | ii. Non-saturation logic |
b — the third state. An ordinary gate drives its output either high or low. A tristate buffer adds a third condition in which the output is effectively disconnected — both output transistors off, presenting a high impedance. This is what makes shared buses possible: many devices connect to the same lines, and all but one hold their outputs in the high-impedance state, so exactly one drives the bus at any moment. Note that high impedance is not a logic level; a voltmeter on such a line reads whatever the other devices or a pull-up impose.
d — why ECL avoids saturation. A saturated bipolar transistor stores excess charge in its base, and that charge must be removed before the device can turn off — the storage-time delay that limits TTL. ECL biases a differential pair so that the transistors are steered between two states while both remain in the active region, never entering saturation. With no stored charge to remove, propagation delays fall to a nanosecond or less, making ECL the fastest bipolar family — at the cost of the highest power consumption, since the tail current flows continuously.
c — the XOR as a controlled inverter. This is the neat one. Take an XOR gate with inputs A and B and examine it one input at a time:
| B | Output |
|---|---|
| 0 | A — passed unchanged |
| 1 | \(\overline{A}\) — inverted |
So B controls whether A is inverted. This is exactly how an adder-subtractor works: XOR each bit of the subtrahend with the mode line, and the same circuit adds when the line is 0 and subtracts by two's complement when it is 1 — the carry-in taking the +1.
a — I2L. Integrated injection logic is built from bipolar transistors, so "bipolar logic" fits, and it is the remaining item. Its interest is historical: by using a multi-collector inverter with current injection instead of resistors, it achieved densities approaching MOS while remaining a bipolar process.
Hence, the correct code is a-iv, b-iii, c-i, d-ii.
Similar Questions
Arrange in ascending order based on power dissipation the following logic families :
(i) ECL
(ii) TTL
(iii) CMOSGiven that for a logic family :
(A) VOH is the maximum output high level voltage
(B) VOL is the maximum input low level voltage
(C) VIH is the minimum input acceptable input high voltage level
(D) VIL is the minimum acceptable input low voltage levelChoose the most appropriate answer from the options given below :
The logic families have fan out more than TTL
A. RTL
B. ECL
C. DTL
D. CMOS
Choose the correct answer from the options given below.
Match the following lists in terms of power dissipation/Gate:
List – I List – II a. BiCMOS i. 6 mW b. ECL ii. 2.75 μW c. CMOS (AHC) iii. 25 mW to 73 mW d. bipolar TTL (F) iv. 17 μw Choose the correct answer from the codes given below:
Arrange the following in terms of decreasing order of power dissipation :
(a) CMOS
(b) ECL
(c) TTL
(d) MOS
The correct sequence of decreasing order of power dissipation is
For a three state TTL following statements are given :
(a) It allows to connect outputs directly.
(b) It allows to connect the inputs directly.
(c) It is used to decrease the switching time.
(d) It is used to increase the switching time in order to interface the peripherals for matching the speed with computer.
Which of the above are correct ?
Match the following in context of Fan out of various families :
List - I List - II (a) DTL (i) 20 (b) TTL (ii) 30 (c) PMOS (iii) 50 (d) CMOS (iv) 5 to 15 Codes :
For wired AND connection we should use :
Match the following :
List - I List - II (a) TTL (i) Consumer maximum power (b) ECL (ii) Highest Packaging Density (c) NMOS (iii) Least power consumption (d) CMOS (iv) Saturated logic Codes :
Match the following lists :
List – I List – II a. IC 7400 i. Quad 2-input NOR gate b. IC 7402 ii. Quad 2-input AND gate c. IC 7408 iii. Quad 2-input OR gate d. IC 7432 iv. Quad 2-input NAND gate
Important Questions from Logic Families
Which of the following pair is correct?
I. RTL – Saturated bipolar logic family
II. ECL – Non-Saturated bipolar logic family
- Which of the following logic families has the maximum noise margin?
The figure of merit of digital IC is defined as:
- Which of the following logic families has the highest packing density?
The figure of merit of logic family is often measured in the unit of:
