The following statements are w.r.t 8086 μp : (a) The width of the address bus for memory referencing is 20 bit Which of them are correct ?
(b) Instruction Pointer (IP) register is an 8-bit register
(c) There are six conditional flags and three control flags
(a) and (c)
(a) is true — the 8086 has a 20-bit physical address. That is what gives it a memory reach of
\(2^{20}=1\,048\,576\ \text{bytes}=1\ \text{MB}\)
and it is produced by the famous segmented scheme: a 16-bit segment register is shifted left four bit positions and added to a 16-bit offset,
\(\text{Physical address}=(\text{Segment}\times16)+\text{Offset}\)
which is exactly how sixteen-bit registers manage to address a megabyte.
(b) is false — the Instruction Pointer is 16 bits, not 8. It must be, since it supplies the offset half of that calculation and has to span a full 64 KB segment. Every general-purpose and pointer register in the 8086 (AX, BX, CX, DX, SI, DI, BP, SP, IP) is 16 bits wide; only the four general registers can additionally be split into 8-bit halves such as AH and AL.
(c) is true — the flag register holds nine flags, six status and three control.
| Type | Flags | Purpose |
|---|---|---|
| Six conditional (status) | CF, PF, AF, ZF, SF, OF | Set by the ALU to report the result |
| Three control | TF, IF, DF | Set by the programmer to steer the processor |
So (a) and (c) hold, giving option 2.
What each control flag does is worth remembering, since these are the ones the programmer writes rather than reads. TF (trap) puts the processor into single-step mode, generating an interrupt after every instruction — the mechanism behind every debugger. IF (interrupt) enables or masks the maskable INTR line, set by STI and cleared by CLI. DF (direction) decides whether string instructions auto-increment or auto-decrement SI and DI.
The comparison with the 8085 makes the differences memorable: the 8085 has an 8-bit data bus, a 16-bit address bus (64 KB) and five flags; the 8086 has a 16-bit data bus, a 20-bit address bus (1 MB), nine flags, and adds the overflow flag OF for signed arithmetic together with the instruction queue that makes it the first pipelined member of the family — the Bus Interface Unit prefetches up to six bytes while the Execution Unit works on the current instruction.
Hence, the correct statements are (a) and (c).
Similar Questions
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
In the following 8051 assembly language program :
MOV A, # 25H
MOV B, # 78H
MUL AB(A) A = 11H, B = 58H
(B) A = 58H, B = 11H
(C) CY = 0 and OV = 1
(D) CY = 1 and OV = 1Choose the most appropriate answer from the options given below :
In a 8051 microcontroller, ACALL (absolute call) instruction has the following interpretation :
(A) It is a two byte instruction
(B) It is a three byte instruction
(C) The target address of the subroutine must be within 2k bytes because only 11 bits of the 2 bytes are used for the address
(D) There is no difference between ACALL and LCALL in terms of saving the program counter on the stack
(E) The target address can be anywhere within 64k bytesChoose the most appropriate answer from the options given below :
Arrange the following interrupts in order of their priority upon reset in case of 8051 micro controller.
(A) INT 0
(B) INT 1
(C) TF 0
(D) TF 1
(E) (R1 + T1)Choose the most appropriate answer from the options given below :
Assertion (A) : For 8086 microprocessor, the CS:IP loaded in the beginning with the required address from which the execution is to be started.
Reason (R) : The microprocessor does not perform the next fetch operation till at least one byte of the instruction queue is emptied.
Which instruction cannot force the 8086 processor to come out of 'HALT' state ?
In 8086 microprocessor which is true ?
(a) Coprocessor is interfaced in MAX mode
(b) Coprocessor is interfaced in MIN mode
(c) I/O can be interfaced in MAX/MIN mode
(d) Supports pipeliningOptions :
Important Questions from Different Processors - Teaching
Match List I with List II:
List I
(Communication Mode)
List II
(Features)
(A) Mode 0 (I) High speed; 8-bit shift register; one
baud rate of f/12
(B) Mode 1 (II) Standard 8-bit UART; variable baud rate using time 1 overflows (C) Mode 2 (III) Multiprocessor 9-bit UART: variable baud rate using time 1 overflows (D) Mode 3 (IV) Multiprocessor 9-bit UART; two
baud rates of f/32 and f/64
Choose the correct answer from the options given below:
Which of the following is/are NOT processor control instructions?
A. STC
B. CMC
C. JNO
D. NOP
E. CWD
Choose the correct answer from the options given below:
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
