Assertion (A) : Any program written for 8080 will run without any changes on 8085. Reason (R) : Any program written for 8086 will run without changes on 8085.
(A) is true, but (R) is false.
Compatibility runs upward, never downward — so the assertion is true and the reason is false, option 3.
Why 8080 code runs on the 8085. The 8085 was designed as an improved, object-code-compatible successor. Its instruction set is a strict superset: every 8080 opcode has the same binary encoding, the same operands and the same effect, and the register model — A, B, C, D, E, H, L, SP, PC and the flags — is unchanged. The 8085 adds only two instructions, RIM and SIM, which use opcodes the 8080 left unassigned. Since a program can contain nothing the newer chip does not recognise, it runs unaltered. Intel's improvements were in hardware — a single 5 V supply instead of three, an on-chip clock generator, a multiplexed bus and vectored interrupts — not in the instruction set.
Why 8086 code cannot run on the 8085. Every reason above is reversed.
| 8085 | 8086 | |
|---|---|---|
| Data width | 8 bits | 16 bits |
| Address bus | 16 bits — 64 KB | 20 bits — 1 MB, segmented |
| Registers | 6 general 8-bit | AX–DX plus SI, DI, BP, SP and four segment registers |
| Instructions | 74 | Far more, including MUL and DIV |
An 8086 program contains opcodes the 8085 has never heard of, references registers that do not exist on it, and uses segment:offset addressing that its 16-bit address bus cannot form. The 8085 would decode the bytes as unrelated 8085 instructions and behave unpredictably.
The relationship the reason gets backwards is that the 8086 was made source-compatible with the 8085 — 8085 assembly language could be mechanically translated and reassembled for the 8086, which is how Intel protected its customers' software investment. But source compatibility upward is not object compatibility downward, and even upward the 8086 does not run 8085 binaries.
The general rule holds across every processor family: a newer device runs its predecessor's code, but the reverse is impossible, since the older chip lacks the hardware the newer instructions were written for.
Hence, (A) is true, but (R) is false.
Similar Questions
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
In the following 8051 assembly language program :
MOV A, # 25H
MOV B, # 78H
MUL AB(A) A = 11H, B = 58H
(B) A = 58H, B = 11H
(C) CY = 0 and OV = 1
(D) CY = 1 and OV = 1Choose the most appropriate answer from the options given below :
In a 8051 microcontroller, ACALL (absolute call) instruction has the following interpretation :
(A) It is a two byte instruction
(B) It is a three byte instruction
(C) The target address of the subroutine must be within 2k bytes because only 11 bits of the 2 bytes are used for the address
(D) There is no difference between ACALL and LCALL in terms of saving the program counter on the stack
(E) The target address can be anywhere within 64k bytesChoose the most appropriate answer from the options given below :
Arrange the following interrupts in order of their priority upon reset in case of 8051 micro controller.
(A) INT 0
(B) INT 1
(C) TF 0
(D) TF 1
(E) (R1 + T1)Choose the most appropriate answer from the options given below :
Assertion (A) : For 8086 microprocessor, the CS:IP loaded in the beginning with the required address from which the execution is to be started.
Reason (R) : The microprocessor does not perform the next fetch operation till at least one byte of the instruction queue is emptied.
Which instruction cannot force the 8086 processor to come out of 'HALT' state ?
The following statements are w.r.t 8086 μp :
(a) The width of the address bus for memory referencing is 20 bit
(b) Instruction Pointer (IP) register is an 8-bit register
(c) There are six conditional flags and three control flagsWhich of them are correct ?
In 8086 microprocessor which is true ?
(a) Coprocessor is interfaced in MAX mode
(b) Coprocessor is interfaced in MIN mode
(c) I/O can be interfaced in MAX/MIN mode
(d) Supports pipeliningOptions :
Important Questions from Different Processors - Teaching
Match List I with List II:
List I
(Communication Mode)
List II
(Features)
(A) Mode 0 (I) High speed; 8-bit shift register; one
baud rate of f/12
(B) Mode 1 (II) Standard 8-bit UART; variable baud rate using time 1 overflows (C) Mode 2 (III) Multiprocessor 9-bit UART: variable baud rate using time 1 overflows (D) Mode 3 (IV) Multiprocessor 9-bit UART; two
baud rates of f/32 and f/64
Choose the correct answer from the options given below:
Which of the following is/are NOT processor control instructions?
A. STC
B. CMC
C. JNO
D. NOP
E. CWD
Choose the correct answer from the options given below:
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
