Arrange the following interrupts in order of their priority upon reset in case of 8051 micro controller. (A) INT 0 Choose the most appropriate answer from the options given below :
(B) INT 1
(C) TF 0
(D) TF 1
(E) (R1 + T1)
(A), (C), (B), (D), (E)
The 8051's default priority follows its vector table in address order, and the external and timer interrupts alternate: INT0, TF0, INT1, TF1, serial — option 1.
| Priority | Interrupt | Vector | Source |
|---|---|---|---|
| 1 (highest) | INT0 | 0003H | External 0, pin P3.2 |
| 2 | TF0 | 000BH | Timer 0 overflow |
| 3 | INT1 | 0013H | External 1, pin P3.3 |
| 4 | TF1 | 001BH | Timer 1 overflow |
| 5 (lowest) | RI + TI | 0023H | Serial port |
The alternation is the point of the question. A natural but wrong guess is to group the two external interrupts together and then the two timers — which is exactly what option 2 offers. The real order interleaves them: external 0, timer 0, external 1, timer 1. Remembering that the priority simply follows the vector addresses upward makes the sequence easy to reconstruct, since the vectors are spaced eight bytes apart from 0003H.
The serial interrupt is last, and it is a single vector shared by both the receive flag RI and the transmit flag TI — which is why the service routine must test both bits to discover which caused the call, and must clear the flag itself, since the hardware does not.
Why "upon reset" is specified. This default order applies only while the IP (Interrupt Priority) register holds its reset value of zero. Setting a bit in IP promotes that source to the high-priority group, and a high-priority interrupt can then interrupt a low-priority routine already in progress. Within a group, the order above still decides which is served when two arrive together.
Two rules govern nesting : a low-priority interrupt cannot interrupt a high-priority one, and no interrupt can interrupt another of its own level. The 8051 therefore supports exactly two levels of nesting.
A related detail worth knowing : the flags for the timer interrupts and for edge-triggered external interrupts are cleared automatically when the service routine is entered, but level-triggered external interrupts and the serial flags are not — a common source of repeated, unintended interrupts.
Hence, the priority order is (A), (C), (B), (D), (E).
Similar Questions
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
In the following 8051 assembly language program :
MOV A, # 25H
MOV B, # 78H
MUL AB(A) A = 11H, B = 58H
(B) A = 58H, B = 11H
(C) CY = 0 and OV = 1
(D) CY = 1 and OV = 1Choose the most appropriate answer from the options given below :
In a 8051 microcontroller, ACALL (absolute call) instruction has the following interpretation :
(A) It is a two byte instruction
(B) It is a three byte instruction
(C) The target address of the subroutine must be within 2k bytes because only 11 bits of the 2 bytes are used for the address
(D) There is no difference between ACALL and LCALL in terms of saving the program counter on the stack
(E) The target address can be anywhere within 64k bytesChoose the most appropriate answer from the options given below :
Assertion (A) : For 8086 microprocessor, the CS:IP loaded in the beginning with the required address from which the execution is to be started.
Reason (R) : The microprocessor does not perform the next fetch operation till at least one byte of the instruction queue is emptied.
Which instruction cannot force the 8086 processor to come out of 'HALT' state ?
The following statements are w.r.t 8086 μp :
(a) The width of the address bus for memory referencing is 20 bit
(b) Instruction Pointer (IP) register is an 8-bit register
(c) There are six conditional flags and three control flagsWhich of them are correct ?
In 8086 microprocessor which is true ?
(a) Coprocessor is interfaced in MAX mode
(b) Coprocessor is interfaced in MIN mode
(c) I/O can be interfaced in MAX/MIN mode
(d) Supports pipeliningOptions :
Important Questions from Different Processors - Teaching
Match List I with List II:
List I
(Communication Mode)
List II
(Features)
(A) Mode 0 (I) High speed; 8-bit shift register; one
baud rate of f/12
(B) Mode 1 (II) Standard 8-bit UART; variable baud rate using time 1 overflows (C) Mode 2 (III) Multiprocessor 9-bit UART: variable baud rate using time 1 overflows (D) Mode 3 (IV) Multiprocessor 9-bit UART; two
baud rates of f/32 and f/64
Choose the correct answer from the options given below:
Which of the following is/are NOT processor control instructions?
A. STC
B. CMC
C. JNO
D. NOP
E. CWD
Choose the correct answer from the options given below:
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
