Assertion (A) : For 8086 microprocessor, the CS:IP loaded in the beginning with the required address from which the execution is to be started. Reason (R) : The microprocessor does not perform the next fetch operation till at least one byte of the instruction queue is emptied.
(A) is correct but (R) is not correct
The assertion describes how the 8086 begins execution correctly; the reason states the queue-refill rule with the wrong number — option 3.
The assertion. The 8086 forms every instruction address from a segment register and an offset:
\(\text{Physical address}=\left(CS\times16\right)+IP\)
On reset CS is set to FFFFH and IP to 0000H, giving FFFF0H — the top of the 1 MB space, where a jump to the real start-up code is placed. To begin execution anywhere else, CS:IP is loaded with the wanted address, and the pair together determine what is fetched next. The statement is a plain and correct description.
Where the reason fails: it should be two bytes, not one. The Bus Interface Unit refills the 6-byte queue whenever at least two bytes are free. The reason is straightforward — the 8086 has a 16-bit data bus, so it fetches a whole word in one bus cycle and cannot usefully perform a fetch unless there is room for both bytes.
| 8086 | 8088 | |
|---|---|---|
| Data bus | 16 bits | 8 bits |
| Queue length | 6 bytes | 4 bytes |
| Refills when free | 2 bytes | 1 byte |
The one-byte rule the reason states belongs to the 8088, whose 8-bit bus fetches a single byte per cycle. Mixing up the two is the error the question is built on, and it is worth remembering that almost every difference between the two chips traces back to that bus width.
Why the queue exists at all. The BIU fetches ahead while the Execution Unit is busy with an instruction, so fetch and execute overlap — a two-stage pipeline, and the 8086's main advance over the 8085. The queue is flushed on every jump, call or interrupt, since the prefetched bytes then belong to a path not taken.
Note also that the reason would not explain the assertion in any case. Loading CS:IP is about where execution starts; the queue-refill threshold is about how prefetching is scheduled thereafter. The two concern different things, so even a correctly stated reason would give option 2 rather than option 1.
Hence, (A) is correct but (R) is not correct.
Similar Questions
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
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MOV A, # 25H
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Which instruction cannot force the 8086 processor to come out of 'HALT' state ?
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In 8086 microprocessor which is true ?
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(d) Supports pipeliningOptions :
Important Questions from Different Processors - Teaching
Match List I with List II:
List I
(Communication Mode)
List II
(Features)
(A) Mode 0 (I) High speed; 8-bit shift register; one
baud rate of f/12
(B) Mode 1 (II) Standard 8-bit UART; variable baud rate using time 1 overflows (C) Mode 2 (III) Multiprocessor 9-bit UART: variable baud rate using time 1 overflows (D) Mode 3 (IV) Multiprocessor 9-bit UART; two
baud rates of f/32 and f/64
Choose the correct answer from the options given below:
Which of the following is/are NOT processor control instructions?
A. STC
B. CMC
C. JNO
D. NOP
E. CWD
Choose the correct answer from the options given below:
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
