Read the following statements : ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.
ST1 is correct and ST2 is wrong.
The 8086 does have a queue, but a queue does not make slow memory harmless — option 4.
ST 1 is plainly true. The 8086 is divided into two independent units:
| Unit | Job |
|---|---|
| BIU — Bus Interface Unit | Fetches instructions and data; holds the 6-byte queue |
| EU — Execution Unit | Decodes and executes from the queue |
While the EU is busy with an instruction, the BIU uses the otherwise idle bus cycles to fetch ahead and fill the queue. This overlap of fetch and execute — a two-stage pipeline — was the 8086's principal advance over the 8085, which fetched and executed strictly in turn. (The 8088, with its 8-bit bus, has a 4-byte queue, since it fills more slowly.)
Why ST 2 is false. The queue hides some memory latency, but it cannot abolish it, for three reasons.
The queue is only six bytes deep. If memory is slow enough, the EU drains it faster than the BIU can refill it, and execution stalls waiting for the next instruction.
Data accesses cannot be prefetched. A queue holds instructions. When an instruction reads or writes an operand, the EU must wait for that access to complete — and slow memory delays it directly.
Every jump empties the queue. On a branch, the prefetched bytes belong to the path not taken and are discarded, so the processor must wait for a fresh fetch from memory at full latency. Since branches occur every few instructions in real code, this happens constantly.
The explicit evidence against ST 2 is the 8086's own READY pin. Slow memory pulls it low, and the processor inserts wait states — idle clock periods during which nothing is executed. The hardware provides a mechanism for being slowed down by slow memory, which would be unnecessary if slow memory did not slow it down.
Flagged because ST 2 is true in the limited sense that the queue reduces the penalty; but as an unqualified statement it is false.
Hence, ST1 is correct and ST2 is wrong.
Similar Questions
Which flag of 8051 works as 1-bit accumulator ?
Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
In the following 8051 assembly language program :
MOV A, # 25H
MOV B, # 78H
MUL AB(A) A = 11H, B = 58H
(B) A = 58H, B = 11H
(C) CY = 0 and OV = 1
(D) CY = 1 and OV = 1Choose the most appropriate answer from the options given below :
In a 8051 microcontroller, ACALL (absolute call) instruction has the following interpretation :
(A) It is a two byte instruction
(B) It is a three byte instruction
(C) The target address of the subroutine must be within 2k bytes because only 11 bits of the 2 bytes are used for the address
(D) There is no difference between ACALL and LCALL in terms of saving the program counter on the stack
(E) The target address can be anywhere within 64k bytesChoose the most appropriate answer from the options given below :
Arrange the following interrupts in order of their priority upon reset in case of 8051 micro controller.
(A) INT 0
(B) INT 1
(C) TF 0
(D) TF 1
(E) (R1 + T1)Choose the most appropriate answer from the options given below :
Assertion (A) : For 8086 microprocessor, the CS:IP loaded in the beginning with the required address from which the execution is to be started.
Reason (R) : The microprocessor does not perform the next fetch operation till at least one byte of the instruction queue is emptied.
Which instruction cannot force the 8086 processor to come out of 'HALT' state ?
The following statements are w.r.t 8086 μp :
(a) The width of the address bus for memory referencing is 20 bit
(b) Instruction Pointer (IP) register is an 8-bit register
(c) There are six conditional flags and three control flagsWhich of them are correct ?
In 8086 microprocessor which is true ?
(a) Coprocessor is interfaced in MAX mode
(b) Coprocessor is interfaced in MIN mode
(c) I/O can be interfaced in MAX/MIN mode
(d) Supports pipeliningOptions :
Important Questions from Different Processors - Teaching
Match List I with List II:
List I
(Communication Mode)
List II
(Features)
(A) Mode 0 (I) High speed; 8-bit shift register; one
baud rate of f/12
(B) Mode 1 (II) Standard 8-bit UART; variable baud rate using time 1 overflows (C) Mode 2 (III) Multiprocessor 9-bit UART: variable baud rate using time 1 overflows (D) Mode 3 (IV) Multiprocessor 9-bit UART; two
baud rates of f/32 and f/64
Choose the correct answer from the options given below:
Which of the following is/are NOT processor control instructions?
A. STC
B. CMC
C. JNO
D. NOP
E. CWD
Choose the correct answer from the options given below:
Which flag of 8051 works as 1-bit accumulator ?
Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
