How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
Four
The 8051's PSW is an 8-bit register, but only four of its bits are conditional flags — bits set automatically by the result of an operation — option 2.
| Bit | Name | Kind |
|---|---|---|
| PSW.7 | CY — carry | Conditional |
| PSW.6 | AC — auxiliary carry | Conditional |
| PSW.5 | F0 — user flag | General purpose |
| PSW.4 | RS1 — register bank select | Control |
| PSW.3 | RS0 — register bank select | Control |
| PSW.2 | OV — overflow | Conditional |
| PSW.1 | — reserved | Unused |
| PSW.0 | P — parity | Conditional |
The distinction the question rests on. A conditional flag is written by the hardware to record something about the outcome of an instruction, and can then be tested by a conditional jump. The other bits are not results at all:
F0 is a free bit the programmer may use as a software flag; nothing in the CPU ever writes it.
RS1 and RS0 are inputs to the CPU, selecting which of the four register banks R0–R7 refers to. They control behaviour rather than reporting it.
Counting only the bits the hardware sets from a result gives CY, AC, OV and P — four.
What each records. CY is the carry out of bit 7, used for multi-byte arithmetic and as the Boolean accumulator for the bit instructions. AC is the carry from bit 3 to bit 4, which exists solely so that the DA A instruction can perform BCD adjustment. OV signals that a signed result has exceeded the range −128 to +127, which is a different condition from CY — the same addition can set one, both, or neither.
P is the odd one out and worth noting. Unlike the others it does not depend on the last operation at all: it is recomputed continuously as the even parity of the accumulator, so it always reflects the current contents of A rather than the outcome of an instruction. It was provided to support serial communication, where a parity bit had to be appended by software.
Hence, the number of conditional flags is four.
Similar Questions
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
In the following 8051 assembly language program :
MOV A, # 25H
MOV B, # 78H
MUL AB(A) A = 11H, B = 58H
(B) A = 58H, B = 11H
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(D) CY = 1 and OV = 1Choose the most appropriate answer from the options given below :
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(B) It is a three byte instruction
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Which instruction cannot force the 8086 processor to come out of 'HALT' state ?
The following statements are w.r.t 8086 μp :
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In 8086 microprocessor which is true ?
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(b) Coprocessor is interfaced in MIN mode
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(d) Supports pipeliningOptions :
Important Questions from Different Processors - Teaching
Match List I with List II:
List I
(Communication Mode)
List II
(Features)
(A) Mode 0 (I) High speed; 8-bit shift register; one
baud rate of f/12
(B) Mode 1 (II) Standard 8-bit UART; variable baud rate using time 1 overflows (C) Mode 2 (III) Multiprocessor 9-bit UART: variable baud rate using time 1 overflows (D) Mode 3 (IV) Multiprocessor 9-bit UART; two
baud rates of f/32 and f/64
Choose the correct answer from the options given below:
Which of the following is/are NOT processor control instructions?
A. STC
B. CMC
C. JNO
D. NOP
E. CWD
Choose the correct answer from the options given below:
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
