In a 8051 microcontroller, ACALL (absolute call) instruction has the following interpretation : (A) It is a two byte instruction Choose the most appropriate answer from the options given below :
(B) It is a three byte instruction
(C) The target address of the subroutine must be within 2k bytes because only 11 bits of the 2 bytes are used for the address
(D) There is no difference between ACALL and LCALL in terms of saving the program counter on the stack
(E) The target address can be anywhere within 64k bytes
(A), (C) and (D) Only
ACALL is two bytes with an 11-bit address, so it reaches only 2 K — but it stacks the return address exactly as LCALL does. Statements (A), (C) and (D), option 1.
(A) and (C) are two aspects of one fact. The instruction occupies two bytes, and of those sixteen bits only eleven carry the destination address; the remaining five are the opcode. Eleven bits reach
\(2^{11}=2048=2\ \text{K}\)
distinct locations. Those eleven bits replace the low eleven bits of the program counter while its top five bits are left unchanged, so the target must lie in the same 2 K page as the instruction following the call.
(E) contradicts (C) and is therefore false. Reaching anywhere in 64 K needs a full sixteen-bit address, which is what LCALL provides — a three-byte instruction carrying the complete destination. Since (C) and (E) cannot both be true, and (C) is right, (E) must go. That alone eliminates options 2 and 4.
(B) is false by the same count: three bytes describes LCALL, not ACALL. That eliminates options 3 and 4, leaving option 1.
(D) is the statement worth pausing on. The two instructions differ in range and size, but not at all in what they do to the stack. Both push the sixteen-bit return address — low byte first, then high byte — and increment the stack pointer by two:
\(SP\leftarrow SP+1,\ \left[SP\right]\leftarrow PC_{low};\qquad SP\leftarrow SP+1,\ \left[SP\right]\leftarrow PC_{high}\)
and a single RET serves both, since it has no way of knowing which call brought it there. This is why the two are freely interchangeable from the subroutine's point of view.
| ACALL | LCALL | |
|---|---|---|
| Size | 2 bytes | 3 bytes |
| Address bits | 11 | 16 |
| Range | 2 K page | Full 64 K |
| Stack behaviour | Identical — two bytes pushed | |
Why ACALL exists at all : it saves one byte of program memory and one machine cycle per call. On a chip with 4 K of on-board ROM those savings mattered, and the assembler resolves the page automatically.
Hence, the correct statements are (A), (C) and (D).
Similar Questions
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
In the following 8051 assembly language program :
MOV A, # 25H
MOV B, # 78H
MUL AB(A) A = 11H, B = 58H
(B) A = 58H, B = 11H
(C) CY = 0 and OV = 1
(D) CY = 1 and OV = 1Choose the most appropriate answer from the options given below :
Arrange the following interrupts in order of their priority upon reset in case of 8051 micro controller.
(A) INT 0
(B) INT 1
(C) TF 0
(D) TF 1
(E) (R1 + T1)Choose the most appropriate answer from the options given below :
Assertion (A) : For 8086 microprocessor, the CS:IP loaded in the beginning with the required address from which the execution is to be started.
Reason (R) : The microprocessor does not perform the next fetch operation till at least one byte of the instruction queue is emptied.
Which instruction cannot force the 8086 processor to come out of 'HALT' state ?
The following statements are w.r.t 8086 μp :
(a) The width of the address bus for memory referencing is 20 bit
(b) Instruction Pointer (IP) register is an 8-bit register
(c) There are six conditional flags and three control flagsWhich of them are correct ?
In 8086 microprocessor which is true ?
(a) Coprocessor is interfaced in MAX mode
(b) Coprocessor is interfaced in MIN mode
(c) I/O can be interfaced in MAX/MIN mode
(d) Supports pipeliningOptions :
Important Questions from Different Processors - Teaching
Match List I with List II:
List I
(Communication Mode)
List II
(Features)
(A) Mode 0 (I) High speed; 8-bit shift register; one
baud rate of f/12
(B) Mode 1 (II) Standard 8-bit UART; variable baud rate using time 1 overflows (C) Mode 2 (III) Multiprocessor 9-bit UART: variable baud rate using time 1 overflows (D) Mode 3 (IV) Multiprocessor 9-bit UART; two
baud rates of f/32 and f/64
Choose the correct answer from the options given below:
Which of the following is/are NOT processor control instructions?
A. STC
B. CMC
C. JNO
D. NOP
E. CWD
Choose the correct answer from the options given below:
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
