In the following 8051 assembly language program : MOV A, # 25H (A) A = 11H, B = 58H Choose the most appropriate answer from the options given below :
MOV B, # 78H
MUL AB
(B) A = 58H, B = 11H
(C) CY = 0 and OV = 1
(D) CY = 1 and OV = 1
(B) and (C) Only
Multiply the two bytes, then place the halves of the 16-bit product where MUL AB puts them.
Step 1 — the product.
\(25_{H}=37,\qquad 78_{H}=120\)
\(37\times120=4440=1158_{H}\)
Step 2 — where the halves go. The 8051 defines MUL AB to leave the low byte in A and the high byte in B:
\(A=58_{H},\qquad B=11_{H}\)
— statement (B). Statement (A) has them interchanged, which is the single most common error with this instruction; the mnemonic order "A, B" tempts one to expect the high byte in A.
Step 3 — the flags. Two rules apply, and they are independent:
| Flag | Rule for MUL AB | Here |
|---|---|---|
| CY | Always cleared — without exception | 0 |
| OV | Set if the product exceeds 255, i.e. if B ≠ 0 | 1 |
The carry is cleared because a multiplication cannot produce a carry in the sense the flag records — there is no ninth bit to carry into, since the whole 16-bit result is retained across the two registers. The overflow flag is used instead, and here it is set because \(B=11_{H}\neq0\), signalling that the result did not fit in a single byte. So statement (C) is correct and (D) is not.
Reading OV correctly matters in practice. A program that multiplies two bytes and expects a byte result should test OV afterwards: if it is clear, B is zero and A alone holds the answer; if it is set, both registers must be used. Testing CY instead would never detect anything, since it is always 0.
The companion instruction follows the opposite convention and is worth remembering alongside: DIV AB leaves the quotient in A and the remainder in B, clears CY, and sets OV only if B was zero — a division by zero.
Hence, the correct statements are (B) and (C).
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.
Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
In a 8051 microcontroller, ACALL (absolute call) instruction has the following interpretation :
(A) It is a two byte instruction
(B) It is a three byte instruction
(C) The target address of the subroutine must be within 2k bytes because only 11 bits of the 2 bytes are used for the address
(D) There is no difference between ACALL and LCALL in terms of saving the program counter on the stack
(E) The target address can be anywhere within 64k bytes
Choose the most appropriate answer from the options given below :
Arrange the following interrupts in order of their priority upon reset in case of 8051 micro controller.
(A) INT 0
(B) INT 1
(C) TF 0
(D) TF 1
(E) (R1 + T1)
Choose the most appropriate answer from the options given below :
Assertion (A) : For 8086 microprocessor, the CS:IP loaded in the beginning with the required address from which the execution is to be started.
Reason (R) : The microprocessor does not perform the next fetch operation till at least one byte of the instruction queue is emptied.
Which instruction cannot force the 8086 processor to come out of 'HALT' state ?
The following statements are w.r.t 8086 μp :
(a) The width of the address bus for memory referencing is 20 bit
(b) Instruction Pointer (IP) register is an 8-bit register
(c) There are six conditional flags and three control flags
Which of them are correct ?
In 8086 microprocessor which is true ?
(a) Coprocessor is interfaced in MAX mode
(b) Coprocessor is interfaced in MIN mode
(c) I/O can be interfaced in MAX/MIN mode
(d) Supports pipelining
Options :
Match List I with List II:
List I (Communication Mode) | List II (Features) | ||
| (A) | Mode 0 | (I) | High speed; 8-bit shift register; one baud rate of f/12 |
| (B) | Mode 1 | (II) | Standard 8-bit UART; variable baud rate using time 1 overflows |
| (C) | Mode 2 | (III) | Multiprocessor 9-bit UART: variable baud rate using time 1 overflows |
| (D) | Mode 3 | (IV) | Multiprocessor 9-bit UART; two baud rates of f/32 and f/64 |
Choose the correct answer from the options given below:
Which of the following is/are NOT processor control instructions?
A. STC
B. CMC
C. JNO
D. NOP
E. CWD
Choose the correct answer from the options given below:
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.
Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.