In 8086 microprocessor which is true ? (a) Coprocessor is interfaced in MAX mode Options :
(b) Coprocessor is interfaced in MIN mode
(c) I/O can be interfaced in MAX/MIN mode
(d) Supports pipelining
(a), (c), (d)
The 8086 runs in one of two modes, selected by a single pin, and that pin decides how much external hardware the system needs.
| MIN mode (MN/MX = 1) | MAX mode (MN/MX = 0) | |
|---|---|---|
| Control signals | Generated by the 8086 itself | Encoded as S2, S1, S0, decoded by the 8288 bus controller |
| Processors on the bus | One | Several — arbitration via RQ/GT lines |
| Coprocessor | Not supported | 8087 / 8089 supported |
(a) is true and (b) false. The 8087 numeric coprocessor watches the 8086's queue status lines and shares the bus with it, and that arrangement needs the request/grant handshake and the queue-status outputs that exist only in MAX mode. In MIN mode those pins carry ordinary control signals instead, so there is no way to attach a coprocessor.
(c) is true. I/O interfacing is independent of the mode: IN and OUT work identically either way, and the difference is only in where the read and write strobes come from — directly from the processor in MIN mode, from the 8288 in MAX mode. Peripherals such as the 8255 and 8259 attach in both.
(d) is true, and it is the 8086's headline architectural feature. The chip is split into two units that work concurrently:
• the Bus Interface Unit fetches instruction bytes ahead of time into a 6-byte queue, and
• the Execution Unit takes bytes from the queue and executes them.
Because fetching and executing overlap, the processor is rarely idle waiting for memory — this is instruction pipelining in its simplest form, and it is what gives the 8086 its speed advantage over the strictly sequential 8085. The queue is flushed whenever a branch is taken, since the prefetched bytes are then useless; that penalty is why branch-heavy code runs proportionally slower.
So (a), (c) and (d) — option 2.
Hence, the correct statements are (a), (c) and (d).
Similar Questions
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
In the following 8051 assembly language program :
MOV A, # 25H
MOV B, # 78H
MUL AB(A) A = 11H, B = 58H
(B) A = 58H, B = 11H
(C) CY = 0 and OV = 1
(D) CY = 1 and OV = 1Choose the most appropriate answer from the options given below :
In a 8051 microcontroller, ACALL (absolute call) instruction has the following interpretation :
(A) It is a two byte instruction
(B) It is a three byte instruction
(C) The target address of the subroutine must be within 2k bytes because only 11 bits of the 2 bytes are used for the address
(D) There is no difference between ACALL and LCALL in terms of saving the program counter on the stack
(E) The target address can be anywhere within 64k bytesChoose the most appropriate answer from the options given below :
Arrange the following interrupts in order of their priority upon reset in case of 8051 micro controller.
(A) INT 0
(B) INT 1
(C) TF 0
(D) TF 1
(E) (R1 + T1)Choose the most appropriate answer from the options given below :
Assertion (A) : For 8086 microprocessor, the CS:IP loaded in the beginning with the required address from which the execution is to be started.
Reason (R) : The microprocessor does not perform the next fetch operation till at least one byte of the instruction queue is emptied.
Which instruction cannot force the 8086 processor to come out of 'HALT' state ?
The following statements are w.r.t 8086 μp :
(a) The width of the address bus for memory referencing is 20 bit
(b) Instruction Pointer (IP) register is an 8-bit register
(c) There are six conditional flags and three control flagsWhich of them are correct ?
Important Questions from Different Processors - Teaching
Match List I with List II:
List I
(Communication Mode)
List II
(Features)
(A) Mode 0 (I) High speed; 8-bit shift register; one
baud rate of f/12
(B) Mode 1 (II) Standard 8-bit UART; variable baud rate using time 1 overflows (C) Mode 2 (III) Multiprocessor 9-bit UART: variable baud rate using time 1 overflows (D) Mode 3 (IV) Multiprocessor 9-bit UART; two
baud rates of f/32 and f/64
Choose the correct answer from the options given below:
Which of the following is/are NOT processor control instructions?
A. STC
B. CMC
C. JNO
D. NOP
E. CWD
Choose the correct answer from the options given below:
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
