BHE of 8086 microprocessor signal is not used to interface the : (a) Even Bank Memory Which of the above referred statements are correct ?
(b) Odd Bank Memory
(c) I/O
(d) DMA
(a), (d)
The 8086 has a 16-bit data bus but a byte-addressable memory, so the memory is split into two banks of 512 KB each, and two signals choose between them.
| Bank | Data lines | Enabled by | Addresses |
|---|---|---|---|
| Even (lower) | D0–D7 | A0 = 0 | 0, 2, 4, … |
| Odd (higher) | D8–D15 | BHE = 0 | 1, 3, 5, … |
So BHE selects the odd bank — it is not used for the even bank, which A0 handles. Statement (a) is therefore correct as a "not used" claim, and statement (b) is wrong.
DMA is the other case where BHE plays no part. During a DMA transfer the 8086 has surrendered the bus: after HOLD is acknowledged with HLDA, the processor tri-states its address, data and control lines, BHE among them. The DMA controller drives the bus itself, so the processor's BHE is simply not involved. Statement (d) is correct.
I/O, by contrast, does use it. A 16-bit I/O port on an odd address needs the higher half of the data bus, and the same bank-selection logic applies to I/O space as to memory. So statement (c) is wrong.
The correct pair is therefore (a) and (d) — option 3.
The four bus-cycle combinations make the scheme clear:
| BHE | A0 | Transfer |
|---|---|---|
| 0 | 0 | Whole word, both banks at once |
| 0 | 1 | Upper byte, odd address |
| 1 | 0 | Lower byte, even address |
| 1 | 1 | None |
The practical consequence — word alignment. A 16-bit word starting at an even address is fetched in a single bus cycle, because both banks are read together. A word starting at an odd address straddles the two banks in the wrong order and needs two bus cycles, doubling the access time. This is why compilers align words on even boundaries, and it is the origin of the alignment rules that persist in every x86 processor since.
Hence, BHE is not used for (a) the even bank and (d) DMA.
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