Assertion (A) : 8086 is 16-bit processor. Reason (R) : Physical address of 8086 will be 32 bits. Select your answer using the codes given below :
(A) is true, but (R) is false
The assertion is true. A processor's "bit width" refers to its data path: the 8086 has 16-bit registers, a 16-bit ALU and a 16-bit external data bus, so it is a 16-bit processor by every usual measure.
The reason is false. The 8086's physical address is 20 bits, not 32, giving a memory reach of
\(2^{20}=1\ \text{MB}\)
With (A) true and (R) false, the code is 3.
How 16-bit registers produce a 20-bit address is the elegant part of the design, and it is worth stating because it is the source of the confusion. A 16-bit segment register is shifted left by four bit positions and added to a 16-bit offset:
\(\text{Physical address}=\left(\text{Segment}\times16\right)+\text{Offset}\)
For example, segment 2000H and offset 0050H give \(20000H+0050H=20050H\) — a 20-bit result from two 16-bit quantities. Each segment is therefore 64 KB (the reach of the offset) and segments may start every 16 bytes, on what is called a paragraph boundary.
| Processor | Data bus | Address bus | Memory |
|---|---|---|---|
| 8085 | 8 | 16 | 64 KB |
| 8086 | 16 | 20 | 1 MB |
| 8088 | 8 external, 16 internal | 20 | 1 MB |
| 80286 | 16 | 24 | 16 MB |
| 80386 | 32 | 32 | 4 GB |
Where 32 bits does belong : the 80386 was the first member of the family with a 32-bit physical address, and hence the first to reach 4 GB. Attributing that to the 8086 telescopes ten years of the architecture's history into one step.
Note also the 8088, the variant used in the original IBM PC: internally identical to the 8086 and still a 16-bit processor, but with an 8-bit external bus so that cheaper 8-bit support chips could be used. It is the clearest illustration that "16-bit processor" describes the internal architecture rather than any single bus width.
Hence, (A) is true but (R) is false — the 8086's physical address is 20 bits.
Similar Questions
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
How many conditional flags are there in the program status word register (psw) in the microcontroller 8051 ?
In the following 8051 assembly language program :
MOV A, # 25H
MOV B, # 78H
MUL AB(A) A = 11H, B = 58H
(B) A = 58H, B = 11H
(C) CY = 0 and OV = 1
(D) CY = 1 and OV = 1Choose the most appropriate answer from the options given below :
In a 8051 microcontroller, ACALL (absolute call) instruction has the following interpretation :
(A) It is a two byte instruction
(B) It is a three byte instruction
(C) The target address of the subroutine must be within 2k bytes because only 11 bits of the 2 bytes are used for the address
(D) There is no difference between ACALL and LCALL in terms of saving the program counter on the stack
(E) The target address can be anywhere within 64k bytesChoose the most appropriate answer from the options given below :
Arrange the following interrupts in order of their priority upon reset in case of 8051 micro controller.
(A) INT 0
(B) INT 1
(C) TF 0
(D) TF 1
(E) (R1 + T1)Choose the most appropriate answer from the options given below :
Assertion (A) : For 8086 microprocessor, the CS:IP loaded in the beginning with the required address from which the execution is to be started.
Reason (R) : The microprocessor does not perform the next fetch operation till at least one byte of the instruction queue is emptied.
Which instruction cannot force the 8086 processor to come out of 'HALT' state ?
The following statements are w.r.t 8086 μp :
(a) The width of the address bus for memory referencing is 20 bit
(b) Instruction Pointer (IP) register is an 8-bit register
(c) There are six conditional flags and three control flagsWhich of them are correct ?
Important Questions from Different Processors - Teaching
Match List I with List II:
List I
(Communication Mode)
List II
(Features)
(A) Mode 0 (I) High speed; 8-bit shift register; one
baud rate of f/12
(B) Mode 1 (II) Standard 8-bit UART; variable baud rate using time 1 overflows (C) Mode 2 (III) Multiprocessor 9-bit UART: variable baud rate using time 1 overflows (D) Mode 3 (IV) Multiprocessor 9-bit UART; two
baud rates of f/32 and f/64
Choose the correct answer from the options given below:
Which of the following is/are NOT processor control instructions?
A. STC
B. CMC
C. JNO
D. NOP
E. CWD
Choose the correct answer from the options given below:
Which flag of 8051 works as 1-bit accumulator ?
Read the following statements :
ST 1 : Queue is provided in 8086.
ST 2 : Slow memory does not degrade speed operation of 8086.Assertion (A) : Any program written for 8080 will run without any changes on 8085.
Reason (R) : Any program written for 8086 will run without changes on 8085.
