Which of the following statements are true regarding the operation of JK flip-flop ? 1. When K input is low and J input is high, the Q output of the flip flop is reset. Which one of the following is true ?
2. When K input is high and J input is low, the output Q of the flip flop is set.
3. When both the inputs K and J are low, the output Q does not change.
4. When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on next positive clock edge.
3 and 4
Check each statement against the characteristic table — the first two have set and reset the wrong way round.
| J | K | Qn+1 | Action |
|---|---|---|---|
| 0 | 0 | Qn | No change |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | \(\overline{Q_{n}}\) | Toggle |
Statement 1 says J high, K low gives a reset — false. J is the set input, so J = 1, K = 0 sets Q to 1.
Statement 2 says K high, J low gives a set — false for the same reason reversed: K is the reset input, so this combination clears Q to 0.
Statement 3 is true. With both inputs low the flip-flop holds its state, which is what makes it a one-bit memory.
Statement 4 is true and describes the toggle mode, the feature the J-K possesses and the S-R does not.
So 3 and 4 — option 2.
The mnemonic that prevents the mix-up : J is for "jump up" (set) and K is for "kill" (clear). Alphabetically, J comes first and corresponds to the higher output.
The characteristic equation encodes all four rows at once:
\(Q_{n+1}=J\overline{Q_{n}}+\overline{K}Q_{n}\)
Substituting J = 1, K = 0 gives \(Q_{n+1}=\overline{Q_{n}}+Q_{n}=1\) — set, confirming statement 1 false. Substituting J = 0, K = 1 gives \(Q_{n+1}=0\) — reset, confirming statement 2 false.
Statement 4's mention of the positive clock edge is important. The toggle mode is exactly where a level-triggered J-K would fail: if the clock stayed high longer than the propagation delay, the output would toggle repeatedly within one pulse — the race-around problem. Edge triggering, or the master-slave arrangement, guarantees precisely one toggle per clock, which is why every practical J-K is edge-triggered.
Hence, the true statements are 3 and 4.
Similar Questions
The truth table of D flip-flop is given below:
C D Qn+1 O X Qn (Last State) $\uparrow$ 0 0 $\uparrow$ 1 1 Choose exact characteristic equation based on above Truth Table
Assertion (A) : Delay flip flop is used to store a single bit either 0 or 1.
Reason (R) : It has only one input, when clock is high and D input is also high, the output resets.
Assertion (A) : Asynchronous sequential circuit is also called event driven circuit.
Reason (R) : Event driven circuit does not have clock to trigger change of state. The states are changed by the change in input signal of the previous stage.
Select your answer using the codes given below.
For the circuit shown below consider the two statements :
Assertion (A) : The circuit is sequential.
Reason (R) : There is a loop in circuit.
Select your answer using the codes given below.
Flip Flop can be used to make :
(a) Latches
(b) Bounce-elimination switches
(c) ADDER
(d) Encoder
Which of the statements given above are correct ?
Under which input condition, the J-K Flip-Flop toggles ?
Read the following statements :
(a) In a J-K Flip Flop, if J = K, the resulting Flip Flop is referred to as a T-type Flip Flop
(b) In a J-K Flip Flop, if J ≠ K, the resulting Flip Flop is referred to as a D-type Flip Flop
(c) An S-R Flip Flop cannot be converted into a T-type Flip Flop since S = R = 1 is not allowed.Which is correct ?
Assertion (A) : D-flip-flops are used as buffer register.
Reason (R) : Flip-flops are free from "race-around" condition.
Select your answer using the codes given below :
In the circuit shown below, the output Y1 and Y2 for the given initial condition Y1 = Y2 = 1 and after four input pulses will be
Read the following statements :
i. Gate is a combinational logic.
ii. JK Flip-flop in toggle mode is not combinational logic.
iii. MSJK FF suffers from race-around.
iv. Counters are sequential circuits.Which is correct ?
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A basic memory storage element in a digital system is:
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