Assertion (A) : Delay flip flop is used to store a single bit either 0 or 1. Reason (R) : It has only one input, when clock is high and D input is also high, the output resets.
(A) is true, but (R) is false.
Assertion — TRUE. A D (delay or data) flip-flop is the basic one-bit storage element. Its characteristic equation is
\(Q_{n+1}=D_n\)
so whatever level is present on D at the active clock edge is captured and held until the next edge. That is exactly what "stores a single bit, 0 or 1" means, and it is why D flip-flops are the cells of registers, shift registers and every pipeline stage.
Reason — contains a true half and a false half, so it fails.
True part: the D flip-flop does have only one data input, which is its great advantage over the S-R type — there is no way to present the forbidden S = R = 1 combination, because R is generated internally as \(\overline{D}\).
False part: with the clock active and D high, the output is SET to 1, not reset. Reset happens when D is low. The reason states the opposite:
| Clock | D | Qn+1 | Action |
|---|---|---|---|
| ↑ | 0 | 0 | reset |
| ↑ | 1 | 1 | set |
| 0 | X | Qn | hold |
So the assertion is correct and the reason is not.
Where the name comes from. Because the output reproduces the input one clock period later, the device delays the data by exactly one cycle — which is what makes a chain of them a shift register, and what lets synchronous design reason about timing in whole clock periods. For the capture to be reliable, D must be steady for the set-up time before the edge and the hold time after it.
Hence, (A) is true, but (R) is false.
Similar Questions
Read the following statements :
i. Gate is a combinational logic.
ii. JK Flip-flop in toggle mode is not combinational logic.
iii. MSJK FF suffers from race-around.
iv. Counters are sequential circuits.Which is correct ?
Which flip-flop can be used as latch ?
In a J-K FF, if J = Q and K = 1 (see figure). Assuming the flip flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be :
Consider the following statements regarding registers and latches :
(A) Registers are made of edge triggered flip-flops whereas latches are made from level triggered flip flops
(B) Registers are temporary storage devices whereas latches are not
(C) A latch employs cross coupled feed back connections
(D) A register stores a binary word whereas a latch does notChoose the most appropriate answer from the options given below :
The toggle condition appears in J-K flip-flop when
A. J=1, K=1
B. J=0, K=0
C. J=0, K=1
D. J=1, K=0
E. J=0, K=1 and J=1, K=0
Choose the correct answer from the options given below :
Match List I with List II
LIST I (Diagram) LIST II (Sequential Circuit) A. 
I. Edge triggered S-R flip flop B. 
II. D Flip flop to SR flip flop C. 
III. Gated Latch clocked flip flop D. 
IV. Gated D Latch Choose the correct answer from the options given below:
The truth table of D flip-flop is given below:
C D Qn+1 O X Qn (Last State) $\uparrow$ 0 0 $\uparrow$ 1 1 Choose exact characteristic equation based on above Truth Table
Assertion (A) : Asynchronous sequential circuit is also called event driven circuit.
Reason (R) : Event driven circuit does not have clock to trigger change of state. The states are changed by the change in input signal of the previous stage.
Select your answer using the codes given below.
For the circuit shown below consider the two statements :
Assertion (A) : The circuit is sequential.
Reason (R) : There is a loop in circuit.
Select your answer using the codes given below.
Flip Flop can be used to make :
(a) Latches
(b) Bounce-elimination switches
(c) ADDER
(d) Encoder
Which of the statements given above are correct ?
Important Questions from Sequential Circuits
The basic sequential logic building block in which the output follows the data input as long as the ENABLE input is active, is
What can be the maximum clock frequency of a 10-bit ripple counter which will not cause a count to skip, considering 10 ns propagation delay for each of the edge-triggered flip flops?
The output of a sequential circuit depends on
The basic building block of a sequential logic circuit is
A 4bit synchronous counter uses flip-flops with a propagation delay time of 25ns each. The maximum possible time required for change of state will be
