Read the following statements : i. Gate is a combinational logic. Which is correct ?
ii. JK Flip-flop in toggle mode is not combinational logic.
iii. MSJK FF suffers from race-around.
iv. Counters are sequential circuits.
i, ii, iv
Statement iii is the false one — the master-slave arrangement exists precisely to cure race-around — so the correct set is i, ii and iv, option 2.
| Statement | Verdict |
|---|---|
| i. A gate is combinational | ✓ Output depends only on present inputs |
| ii. JK in toggle mode is not combinational | ✓ The output depends on its own previous state |
| iii. MSJK suffers race-around | ✗ It is the cure, not a victim |
| iv. Counters are sequential | ✓ A counter's output is its history |
What race-around is. In a simple level-triggered JK flip-flop with J = K = 1, the output should toggle once per clock. But the output feeds back to the input gates, and if the clock stays high for longer than the propagation delay of the flip-flop, the new output toggles the device again — and again — for as long as the clock remains high. The final state is then unpredictable. The condition for the fault is
\(t_{pulse}\gt t_{pd}\)
and since propagation delays are only nanoseconds, avoiding it by narrowing the clock pulse is impractical.
How master-slave removes it. Two latches are cascaded and driven by complementary clocks. While the clock is high the master accepts the inputs and the slave is isolated; when the clock falls the master is isolated and the slave copies it to the output. At no instant are input and output paths open together, so the new output cannot race back to the input — regardless of how long the clock stays high. That is exactly what statement iii denies.
The combinational-against-sequential distinction is what statements i, ii and iv test, and one question settles it: does the circuit's output depend on anything other than its present inputs? A gate's does not — the same inputs always give the same output. A toggling JK flip-flop's does: with J = K = 1 held constant, the output alternates, so the inputs alone do not determine it. A counter is the same idea extended — its whole purpose is to remember how many pulses have arrived.
A footnote on the master-slave cure : it is not perfect. The master is transparent for the whole time the clock is high, so a brief glitch on J or K during that window can be captured and held — the "ones-catching" defect, which edge-triggered flip-flops avoid.
Hence, the correct statements are i, ii and iv.
Similar Questions
Which flip-flop can be used as latch ?
In a J-K FF, if J = Q and K = 1 (see figure). Assuming the flip flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be :
Consider the following statements regarding registers and latches :
(A) Registers are made of edge triggered flip-flops whereas latches are made from level triggered flip flops
(B) Registers are temporary storage devices whereas latches are not
(C) A latch employs cross coupled feed back connections
(D) A register stores a binary word whereas a latch does notChoose the most appropriate answer from the options given below :
The toggle condition appears in J-K flip-flop when
A. J=1, K=1
B. J=0, K=0
C. J=0, K=1
D. J=1, K=0
E. J=0, K=1 and J=1, K=0
Choose the correct answer from the options given below :
Match List I with List II
LIST I (Diagram) LIST II (Sequential Circuit) A. 
I. Edge triggered S-R flip flop B. 
II. D Flip flop to SR flip flop C. 
III. Gated Latch clocked flip flop D. 
IV. Gated D Latch Choose the correct answer from the options given below:
The truth table of D flip-flop is given below:
C D Qn+1 O X Qn (Last State) $\uparrow$ 0 0 $\uparrow$ 1 1 Choose exact characteristic equation based on above Truth Table
Assertion (A) : Delay flip flop is used to store a single bit either 0 or 1.
Reason (R) : It has only one input, when clock is high and D input is also high, the output resets.
Assertion (A) : Asynchronous sequential circuit is also called event driven circuit.
Reason (R) : Event driven circuit does not have clock to trigger change of state. The states are changed by the change in input signal of the previous stage.
Select your answer using the codes given below.
For the circuit shown below consider the two statements :
Assertion (A) : The circuit is sequential.
Reason (R) : There is a loop in circuit.
Select your answer using the codes given below.
Flip Flop can be used to make :
(a) Latches
(b) Bounce-elimination switches
(c) ADDER
(d) Encoder
Which of the statements given above are correct ?
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