Assertion (A) : D-flip-flops are used as buffer register. Reason (R) : Flip-flops are free from "race-around" condition. Select your answer using the codes given below :
(A) is true, but (R) is false.
(A) is true, but (R) is false — option (C).
The assertion is true. A buffer register simply holds a word until it is needed, and a bank of D flip-flops sharing a common clock does exactly that. On the active clock edge each flip-flop copies its input to its output and holds it until the next edge:
\(Q_{n+1}=D\)
Because that characteristic equation has no forbidden combination and no toggling, D flip-flops are the natural storage element — and this is precisely how the 74LS273, 74LS373 and every register inside a processor are built.
Why the reason is false. (R) says “flip-flops are free from race-around condition”, stated as a blanket claim about flip-flops in general. That is not so. Race-around is a genuine defect of the level-triggered JK flip-flop :
| Stage | What happens |
|---|---|
| Condition | J = K = 1 and the clock is held high for longer than the propagation delay |
| Effect | The output toggles repeatedly for as long as the clock stays high |
| Result | The final state depends on when the clock falls — it is indeterminate |
| Requirement to avoid it | The clock’s high time would have to satisfy \(t_{pd}<t_{clk}<T\), an impractical constraint |
The condition is real enough to have driven two standard cures, which is itself proof that flip-flops are not inherently free of it :
| Cure | How it works |
|---|---|
| Master-slave | Two latches in series clocked in antiphase, so the output can change only once per clock cycle |
| Edge triggering | The device responds only at the instant of the clock transition, so there is no window in which to toggle |
The correct statement would be narrower: D flip-flops are free from race-around, because with a single data input the condition J = K = 1 cannot arise. That is a property of the D type, not of flip-flops as a class — and generalising it is exactly the error (R) makes.
The test to apply in assertion-reason items: a reason stated as a universal claim fails if a single counter-example exists. Here the level-triggered JK is that counter-example, so (R) is false while (A) stands, giving code (C).
Hence, the answer is (A) is true, but (R) is false.
Similar Questions
The truth table of D flip-flop is given below:
C D Qn+1 O X Qn (Last State) $\uparrow$ 0 0 $\uparrow$ 1 1 Choose exact characteristic equation based on above Truth Table
Assertion (A) : Delay flip flop is used to store a single bit either 0 or 1.
Reason (R) : It has only one input, when clock is high and D input is also high, the output resets.
Assertion (A) : Asynchronous sequential circuit is also called event driven circuit.
Reason (R) : Event driven circuit does not have clock to trigger change of state. The states are changed by the change in input signal of the previous stage.
Select your answer using the codes given below.
For the circuit shown below consider the two statements :
Assertion (A) : The circuit is sequential.
Reason (R) : There is a loop in circuit.
Select your answer using the codes given below.
Flip Flop can be used to make :
(a) Latches
(b) Bounce-elimination switches
(c) ADDER
(d) Encoder
Which of the statements given above are correct ?
Under which input condition, the J-K Flip-Flop toggles ?
Read the following statements :
(a) In a J-K Flip Flop, if J = K, the resulting Flip Flop is referred to as a T-type Flip Flop
(b) In a J-K Flip Flop, if J ≠ K, the resulting Flip Flop is referred to as a D-type Flip Flop
(c) An S-R Flip Flop cannot be converted into a T-type Flip Flop since S = R = 1 is not allowed.Which is correct ?
Which of the following statements are true regarding the operation of JK flip-flop ?
1. When K input is low and J input is high, the Q output of the flip flop is reset.
2. When K input is high and J input is low, the output Q of the flip flop is set.
3. When both the inputs K and J are low, the output Q does not change.
4. When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on next positive clock edge.Which one of the following is true ?
In the circuit shown below, the output Y1 and Y2 for the given initial condition Y1 = Y2 = 1 and after four input pulses will be
Read the following statements :
i. Gate is a combinational logic.
ii. JK Flip-flop in toggle mode is not combinational logic.
iii. MSJK FF suffers from race-around.
iv. Counters are sequential circuits.Which is correct ?
Important Questions from Sequential Circuits
A basic memory storage element in a digital system is:
The basic sequential logic building block in which the output follows the data input as long as the ENABLE input is active, is
What can be the maximum clock frequency of a 10-bit ripple counter which will not cause a count to skip, considering 10 ns propagation delay for each of the edge-triggered flip flops?
The output of a sequential circuit depends on
The basic building block of a sequential logic circuit is
