Which flip-flop can be used as latch ?
D- Flip-flop
D flip-flop — option (D).
What a latch is. A latch is a level-sensitive one-bit store: while its enable line is active the output follows the input, and when the enable goes inactive the last value is held. A D flip-flop used this way is the D latch or transparent latch — the standard data-storage element, and the reason the 7475 and 74LS373 exist.
| Phase | Enable | Behaviour |
|---|---|---|
| Transparent | Active | \(Q=D\) — the output tracks the input continuously |
| Hold (latched) | Inactive | Q retains whatever D was at the moment of the transition |
Why the D type is the natural choice. Its characteristic equation is simply \(Q_{n+1}=D\). That has three consequences that matter for storage :
| Property | Consequence |
|---|---|
| One data input | Nothing to encode — the bit to be stored is applied directly |
| No forbidden state | Unlike the SR type, there is no input combination that produces an indeterminate output |
| No toggling | Unlike the JK and T types, the output cannot flip on its own while enabled |
Why the other three are weaker answers. The SR latch is genuinely the primitive from which all latches are built, and internally a D latch is an SR latch with an inverter forcing \(S=D\) and \(R=\overline{D}\) — but as a user-facing store it has the forbidden condition S = R = 1, which is exactly what the D arrangement is designed to remove. The JK type toggles when J = K = 1 and suffers race-around in its level-triggered form, and the T type only toggles, so neither can simply hold a presented value.
The distinction that examiners test here is latch against flip-flop :
| Latch | Flip-flop | |
|---|---|---|
| Triggered by | A level | An edge |
| Output during active clock | Follows the input — transparent | Changes only at the transition |
| Typical use | Bus and address latching, the 74LS373 | Synchronous registers, counters, the 74LS374 |
A bank of eight D latches is what holds the low-order address in an 8085 system while ALE de-multiplexes the AD bus — the single most common latch in the syllabus.
Hence, the answer is D flip-flop.
Similar Questions
Read the following statements :
i. Gate is a combinational logic.
ii. JK Flip-flop in toggle mode is not combinational logic.
iii. MSJK FF suffers from race-around.
iv. Counters are sequential circuits.Which is correct ?
The truth table of D flip-flop is given below:
C D Qn+1 O X Qn (Last State) $\uparrow$ 0 0 $\uparrow$ 1 1 Choose exact characteristic equation based on above Truth Table
Assertion (A) : Delay flip flop is used to store a single bit either 0 or 1.
Reason (R) : It has only one input, when clock is high and D input is also high, the output resets.
Assertion (A) : Asynchronous sequential circuit is also called event driven circuit.
Reason (R) : Event driven circuit does not have clock to trigger change of state. The states are changed by the change in input signal of the previous stage.
Select your answer using the codes given below.
For the circuit shown below consider the two statements :
Assertion (A) : The circuit is sequential.
Reason (R) : There is a loop in circuit.
Select your answer using the codes given below.
Flip Flop can be used to make :
(a) Latches
(b) Bounce-elimination switches
(c) ADDER
(d) Encoder
Which of the statements given above are correct ?
Under which input condition, the J-K Flip-Flop toggles ?
Read the following statements :
(a) In a J-K Flip Flop, if J = K, the resulting Flip Flop is referred to as a T-type Flip Flop
(b) In a J-K Flip Flop, if J ≠ K, the resulting Flip Flop is referred to as a D-type Flip Flop
(c) An S-R Flip Flop cannot be converted into a T-type Flip Flop since S = R = 1 is not allowed.Which is correct ?
Which of the following statements are true regarding the operation of JK flip-flop ?
1. When K input is low and J input is high, the Q output of the flip flop is reset.
2. When K input is high and J input is low, the output Q of the flip flop is set.
3. When both the inputs K and J are low, the output Q does not change.
4. When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on next positive clock edge.Which one of the following is true ?
Assertion (A) : D-flip-flops are used as buffer register.
Reason (R) : Flip-flops are free from "race-around" condition.
Select your answer using the codes given below :
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