The following 8051 assembly program is given. Answer the questions based on it.

Line No.	Mnemonics
1	MOV SP, #4F H
2	SET B PSW.3
3	MOV R0, #25H
4	MOV R1, #0AH
5	MOV R2, #06H
6	PUSH 8
7	PUSH 9
8	PUSH 0AH
	.
	.
	.
V	V
20	POP 8

The rule for the 8051 stack. The stack grows upward in internal RAM, and on every PUSH the sequence is:

1. increment SP by one, then 2. write the data byte at the new address in SP.

So SP always points to the byte most recently stored — the current top of stack — and the next free location is SP + 1.

Apply it to this program. Line 1 set SP = 4FH. The first push in the program is line 6, \(\texttt{PUSH 8}\). When it executes:

\(SP \leftarrow 4FH + 1 = 50H\)

and the data byte is then written to address 50H.

Therefore the first data byte is stored at 50H, not at 4FH — location 4FH is never written to at all; it is merely the starting marker below the stack area.

Why pre-increment matters. Contrast this with a POP, which reverses the order: read the byte at SP first, then decrement SP. Together the two rules keep SP consistently pointing at the last valid entry, so a stack that has been pushed and popped equally often returns SP to its original value. Following the same rule, the next push (line 7) will use 51H and the one after that 52H, which is how the later questions in this set are answered.

Checking the distractors. 4FH ignores the pre-increment; 51H and 52H correspond to the second and third pushes.

Hence, the first data byte is stored at memory location 50H.

This question needs three separate facts to be combined: which register bank is active, what that makes the direct address of R0, and how PUSH works.

Step 1 — which register bank? The instruction \(\texttt{SETB PSW.3}\) sets RS0 = 1 while RS1 (PSW.4) remains 0. The bank-select bits therefore read RS1 RS0 = 01, which selects register bank 1.

So in bank 1: R0 = address 08H, R1 = 09H, R2 = 0AH.

Step 2 — what is at address 08H? Line 3, \(\texttt{MOV R0, \#25H}\), loads the immediate value 25H into R0 — which, with bank 1 active, physically means RAM location 08H now holds 25H.

Step 3 — what does PUSH 8 push? PUSH takes a direct address as its operand, not a register name. \(\texttt{PUSH 8}\) therefore pushes the byte stored at address 08H, which is 25H. (This is why the bank matters: had bank 0 been active, R0 would be at 00H and address 08H would be R0 of bank 1 instead.)

Step 4 — where does it land? SP was 4FH, so it is pre-incremented to 50H and the byte is written there:

\(50H \leftarrow 25H\)

Why the distractors are wrong. 0AH is the value in R1 (address 09H), pushed later by line 7; 06H is in R2 (address 0AH); 4FH is the old SP value, which is never itself pushed.

Hence, memory location 50H holds 25H.

 State of the register bank. With \(\texttt{SETB PSW.3}\) having selected bank 1, the registers map to internal RAM as R0 → 08H, R1 → 09H, R2 → 0AH, and lines 3–5 have loaded them:

Trace the pushes.

Line 6, \(\texttt{PUSH 8}\): SP goes 4FH → 50H, and the byte at address 08H (25H) is written to 50H.

Line 7, \(\texttt{PUSH 9}\): SP is pre-incremented 50H → 51H, and the byte at direct address 09H is written there. Address 09H holds 0AH (put there by \(\texttt{MOV R1, \#0AH}\)), so

\(51H \leftarrow 0AH, \qquad SP = 51H\)

Both parts of the answer therefore read 51H and 0AH.

The trap in this question. The value 0AH appears twice in the program in two completely different roles — as the data loaded into R1, and as the address of R2 in bank 1. Reading \(\texttt{PUSH 9}\) you must remember the operand 9 is an address (09H = R1), while the byte it contains, 0AH, is data. The distractors exploit exactly this: option 1 offers 25H (the previous push), option 2 gives an SP of 52H (one push too many), option 3 gives the previous SP with the new data.

Stack picture after line 7 (SP marks the top): 50H = 25H, 51H = 0AH ← SP.

Hence, after line 7 the SP register holds 51H and stack location 51H contains 0AH.

The instruction on line 1. \(\texttt{MOV SP, \#4FH}\) — the "#" marks 4FH as an immediate constant, and SP is the Stack Pointer, a special-function register at address 81H. The instruction therefore writes the byte 4FH straight into SP.

What SP holds afterwards. No PUSH, POP, CALL or RET has executed yet, and only those operations change SP. So immediately after line 1,

\(SP = 4FH\)

Why the program does this at all. On reset the 8051 initialises SP to 07H, which means the very first PUSH writes to 08H — the start of register bank 1. Any program that uses more than the default bank 0 must therefore move the stack out of the way, and 4FH puts it in the general-purpose scratchpad area (30H–7FH), safely above the register banks (00H–1FH) and the bit-addressable region (20H–2FH).

Where it goes next. Because the 8051 stack grows upward and SP is pre-incremented on a push, the first byte pushed will land at 50H, not at 4FH — SP always points at the last byte written, i.e. the current top of stack. That distinction is what the following questions in this set test. With SP at 4FH, the available stack space runs up to 7FH, i.e. 48 bytes.

Ruling out the distractors. 5FH, 3FH and 6FH would each require a different immediate operand; the instruction as written moves exactly 4FH.

Hence, after line 1 the SP register contains 4FH.

How the 8051 stack unwinds. The stack is LIFO — last in, first out. A POP reverses a PUSH: it reads the byte at the address currently in SP, writes it to the destination, and then decrements SP.

State of the stack before the POP. With bank 1 selected (R0 → 08H, R1 → 09H, R2 → 0AH holding 25H, 0AH and 06H respectively), the three pushes have filled the stack as:

Execute POP 8. The destination operand 8 is the direct address 08H, which with bank 1 active is register R0. The instruction takes the byte at the top of the stack — 06H at address 52H — writes it into 08H, and decrements SP to 51H. Therefore

\(R0 = 06H\)

The point being tested. R0 originally held 25H, and 25H is still sitting at the bottom of this group of pushes (50H). Because the stack is LIFO, the first POP returns the last value pushed, not the value that R0 started with. Restoring registers correctly therefore requires the POPs to be written in the exact reverse order of the PUSHes — pop 0AH, then 9, then 8 — otherwise the register contents are swapped, which is a classic bug in interrupt service routines.

Distractors. 0AH would be the result of the second pop, 25H of the third, and 4FH is the initial SP value, which is never a data byte.

Hence, after line 20 (POP 8) register R0 contains 06H.