A microprocessor is a semiconductor chip fabricated with entire central processing unit (CPU) on it. It is a programmable device that accepts binary data from an input device, processes the data according to the instructions stored in the memory and provides results as output. Basically microprocessor performs two functions - (a) Fetches an instruction from the memory and (b) Performs the operation specified by the instruction. There are special inputs to the microprocessor called interrupts. External devices use these interrupts to get the microprocessor attention. A micro computer can be built by using 8085 microprocessor along with many other chips such as 8155, 8255, 8279, 8253, 8257, 8259, 8251 etc. 8085 microprocessor is 8-bit microprocessor which has 8-bit data registers where as 8086 is a 16-bit microprocessor.

The name says exactly what the technique does. In memory-mapped I/O each peripheral register is given an address out of the processor's ordinary memory space, so the CPU talks to it with the same instructions it uses for memory — option 4.

The alternative is I/O-mapped I/O, also called isolated or peripheral-mapped I/O, in which peripherals live in a separate address space of their own, reached only by the dedicated IN and OUT instructions. Option 1 names precisely that opposite scheme, which is why it is the attractive wrong answer here.

The 8085 supports both, and the IO/M pin is what distinguishes them: the address decoder is simply wired to include or ignore that line. If the decoder ignores IO/M entirely, the device answers to a memory address and the scheme is memory-mapped.

Why anyone would spend memory addresses on peripherals. The gain is the full instruction set. A memory-mapped port can be tested with ANA M, incremented with INR M or added to the accumulator directly, whereas an isolated port must first be brought in with IN before anything can be done to it. That flexibility is why almost every modern processor — ARM and RISC-V among them — is purely memory-mapped and has no separate I/O space at all; the x86 family, with its IN/OUT instructions, is the notable survivor of the other tradition.

Options 2 and 3, "ported I/O" and "dedicated I/O", are not standard terms for either scheme.

Hence, the technique is called memory-mapped I/O.

The 8085 flag register holds five flags, and each watches a different property of the result.

The sign flag is simply a copy of bit 7 of the result, which is exactly what the question describes, so the answer is option 1.

Why bit 7 is called the sign. In two's-complement arithmetic an 8-bit byte represents −128 to +127, and the most significant bit carries the sign: 0 for positive, 1 for negative. Copying that bit into a flag lets the programmer branch on the sign of a result without any further testing, using JM (jump if minus) or JP (jump if plus).

The distinction from the carry flag is the usual trap. The carry flag records a carry out of the byte — information that has left the result — whereas the sign flag records a bit that is still inside it. Example:

MVI A, 70H   ADI 20H   →   result 90H

Here CY = 0, because nothing carried out of bit 7, but S = 1, because the result's bit 7 is 1. Read as signed numbers, 112 + 32 has overflowed past +127 into −112 — which is precisely why signed and unsigned interpretations must never be mixed.

A practical note. The flags are the upper byte of the PSW (program status word), so PUSH PSW saves the accumulator and all five flags together — essential at the start of an interrupt service routine, since almost any instruction there would otherwise destroy the flags the interrupted program was relying on. Note also that logical instructions such as ANA and ORA affect the flags too, and that INR and DCR deliberately leave the carry flag untouched.

Hence, the MSB of the result is stored in the sign status flag.

A T-state is one clock period, so the whole calculation is two lines.

Step 1 — find the clock period.

\(T=\dfrac{1}{f}=\dfrac{1}{5\times10^{6}}=0.2\times10^{-6}\ \text{s}=0.2\ \mu\text{s}\)

Step 2 — multiply by the number of T-states.

\(t=18\times0.2\ \mu\text{s}=3.6\ \mu\text{s}\)

which is option 2.

The vocabulary the 8085 uses for timing is worth fixing, because these three terms are constantly confused:

An opcode fetch takes 4 T-states (6 for some instructions), while a memory read or write takes 3. An 18 T-state instruction is therefore a long one — CALL, for example, is 18 T-states in five machine cycles, since it must fetch a three-byte instruction and then push the return address onto the stack.

One caution about the word "clock". The 8085 contains an internal divide-by-two, so a crystal connected across X₁ and X₂ runs at twice the operating frequency — a 6 MHz crystal gives a 3 MHz internal clock. Here the question specifies the clock frequency itself as 5 MHz, so it is the operating frequency and no halving applies. Had it said "crystal frequency", the answer would have been double, at 7.2 μs.

The general form worth memorising :

\(\text{Execution time}=\dfrac{\text{Number of T-states}}{\text{Clock frequency}}\)

This is the standard route to computing software delay loops, where the T-state counts of DCR, JNZ and the rest are added up and multiplied by the clock period to obtain the delay produced.

Hence, the execution time is 3.6 μs.

Two facts settle this: PUSH always moves a register pair, and it copies rather than moves.

The 8085 stack is 16 bits wide in operation, so the four permitted operands — PUSH B, PUSH D, PUSH H and PUSH PSW — each transfer two bytes. Naming "B" is shorthand for the BC pair, and the C register goes along with it. That eliminates option 1.

The registers are not disturbed. Their contents are copied into memory; nothing writes back to them, so B and C hold exactly what they held before. That eliminates options 2 and 4, leaving option 3.

What actually happens, cycle by cycle. The stack grows downward in memory, and the high byte goes first:

So after the instruction the stack pointer has fallen by 2:

\(SP_{new}=SP_{old}-2\)

The matching POP B reverses the sequence — C is retrieved first, then B, and SP rises by 2. PUSH B takes 12 T-states, POP B only 10, the extra time being the two decrements.

Why the stack is used. It is the standard way to preserve registers across a subroutine or an interrupt service routine, so that the called code may use them freely:

PUSH B   PUSH D   PUSH H   PUSH PSW   …   POP PSW   POP H   POP D   POP B

The order must be reversed on the way out, because the stack is last-in-first-out; getting it wrong swaps register contents and produces bugs that are very hard to trace. Note also that the stack shares ordinary read/write memory, so LXI SP must set the pointer to the top of available RAM before any PUSH is executed, and a deeply nested program can otherwise let the stack grow down into its own data.

Hence, PUSH B causes the contents of registers B and C to be copied in the stack.

What the HALT state is. Executing HLT stops the 8086's instruction execution. The processor floats its buses, stops fetching, and simply waits — a low-power idle from which only an external event can rescue it.

Three signals are candidates, and only two work.

Why HOLD is the exception, and it is a matter of purpose. HOLD is a bus request, not an execution request. A DMA controller raises HOLD to borrow the buses; the 8086 answers with HLDA and tri-states its bus drivers. Nothing about that sequence asks the processor to execute anything. When the device drops HOLD, the 8086 takes its buses back and returns to exactly the halted state it was in. So the answer is option 4.

The contrast with the interrupt lines. An interrupt is a request for processing: the processor must push the flags, CS and IP, fetch the vector from the interrupt vector table at the bottom of memory, and execute the service routine. Since that is execution, HALT necessarily ends. Note the qualification on INTR — it is maskable, so it only works if the interrupt flag has been set by STI. NMI on pin 17 cannot be masked and will always wake the processor, which is why it is reserved for events such as a power-failure warning.

The practical use of HLT. A program that has nothing to do until an event occurs executes HLT rather than spinning in a polling loop — the processor consumes less power and generates no bus traffic, and the interrupt that signals the event brings it straight back to life. The same idea survives in every modern CPU as the halt or wait-for-interrupt instruction at the heart of an idle task.

Hence, the signal that cannot bring the 8086 out of HALT is HOLD.