Assertion (A) : In serial communication system, when the transmission of data goes in both ways, it is called full-duplex system. Now if two micro processors are connected in full duplex mode, the amount of data transmitted will be double to the amount of data in half-duplex mode connection. Reason (R) : When the transmission of data goes in one way, it is called half-duplex system and when the data moves in both ways, it is called full duplex system.
(A) is false, but (R) is true.
(A) is false, but (R) is true — option (D).
The reason is true and is simply the standard definition :
| Mode | Direction of transfer | Example |
|---|---|---|
| Simplex | One way only, never reversed | Broadcast radio, keyboard to computer |
| Half duplex | Both ways, but only one at a time | Walkie-talkie, older RS-485 buses |
| Full duplex | Both ways simultaneously | Telephone, RS-232 with separate TxD and RxD lines |
The assertion opens correctly and then overreaches. Its first clause — transmission going both ways is called full duplex — is right. The claim that fails is the second: that connecting two microprocessors in full duplex makes the amount of data transmitted double what half duplex would carry. That is an idealisation, not a fact, and it breaks down for several independent reasons :
| Why the doubling does not follow | Explanation |
|---|---|
| It assumes traffic is symmetric | Doubling requires both directions to be busy at once. Most real exchanges are request-and-response — one side waits while the other talks — and an idle return channel carries nothing |
| Half duplex is not half-rate | A half-duplex link uses the whole channel in whichever direction it is transmitting. Over a period it interleaves the two directions rather than halving each |
| Protocol overhead differs | Full duplex removes turnaround delay and acknowledgement waits, so the realised gain is usually better than a naive halving in interactive traffic and worse than double in bulk one-way transfer |
| The bottleneck may be elsewhere | Processor speed, buffer size or baud rate can limit throughput before the duplex mode does |
So (A) states a definition correctly and then attaches an unsupported quantitative claim to it. A statement that is right in part and wrong in part is false as a whole, which is what makes the code (D).
The lesson for assertion-reason items. Where an assertion contains two clauses, both must hold. Examiners construct these by pairing a familiar true definition with a plausible-sounding numerical consequence, relying on the candidate to accept the second because the first is obviously right. Read to the end of the sentence before judging it.
Where this appears in hardware: the 8085 family uses the 8251A USART, whose separate transmitter and receiver sections allow genuine full-duplex working; the mode is chosen by the mode instruction word written during initialisation.
Hence, the answer is (A) is false, but (R) is true.
Similar Questions
A microprocessor is a semiconductor chip fabricated with entire central processing unit (CPU) on it. It is a programmable device that accepts binary data from an input device, processes the data according to the instructions stored in the memory and provides results as output. Basically microprocessor performs two functions - (a) Fetches an instruction from the memory and (b) Performs the operation specified by the instruction. There are special inputs to the microprocessor called interrupts. External devices use these interrupts to get the microprocessor attention. A micro computer can be built by using 8085 microprocessor along with many other chips such as 8155, 8255, 8279, 8253, 8257, 8259, 8251 etc. 8085 microprocessor is 8-bit microprocessor which has 8-bit data registers where as 8086 is a 16-bit microprocessor.
The following 8051 assembly program is given. Answer the questions based on it.
Line No. Mnemonics 1 MOV SP, #4F H 2 SET B PSW.3 3 MOV R0, #25H 4 MOV R1, #0AH 5 MOV R2, #06H 6 PUSH 8 7 PUSH 9 8 PUSH 0AH . . . V V 20 POP 8 $D_7$ $D_6$ $D_5$ $D_4$ $D_3$ $D_2$ $D_1$ $D_0$ In 8255 programmable peripheral interface device, if the port A and port B are to be set in a hand shake mode along with port C, what are the bits in the 8 bit control word to be set as 0 1 0.
The number system for the machine code of the microprocessor 8085 is
Which of the options in a multipurpose instruction used to implement the interrupt of 8085 and serial data input ?
Both 8155 and 8255 programmable peripheral interface ICs have the following common features :
(i) Programmable I/Os
(ii) Either port A or Port B can be set as either input or output ports.
(iii) One 14-bit down counter
(iv) AD0 – AD7 are multiplexed address/datalines.Each instruction in an assembly program has the following fields :
(i) Lable field
(ii) Operand field
(iii) Comment field
(iv) Mnemonic fieldPlease write the proper sequence of fields :
The mnemonic of 8085 processor indicate :
List – I List – II a. RLC i. Rotate Accumulator Right through carry b. RRC ii. Rotate Accumulator Left through carry c. RAR iii. Rotate Accumulator Left d. RAL iv. Rotate Accumulator Right Codes :
Match the following :
List – I (Pin terminals) List – II (Applications) a. SID, SOD i. Wait state b. READY ii. Serial data transfer c. TRAP iii. Address Latch Control d. ALE iv. Interrupt Codes :
The assembler directive used to give name to some value or symbol for 8086 ASM-86 is
Important Questions from Microprocessors
An 8086 address bus is a/an _____ -bit bus
Program counter for any counter:
In the pin out configuration of the 8085 microprocessor, the sequential input data is represented by
Which of the following functions is not performed by a microprocessor?
Match the columns.
Pin
Description
a. D 0-D 7
1. Reset Input
b. RESET
2. Data Lines
c. A 0,A 1
3. Internal Address
