The conversion time for an 8-bit successive approximation ADC which is driven by 1-MHz clock is :
9 μs
A successive-approximation converter performs a binary search, one bit per clock. The SAR sets the MSB, the internal DAC output is compared with the input, the bit is kept if the DAC output is still below the input and cleared otherwise, and the process repeats down to the LSB. An n-bit conversion therefore needs n clock cycles for the bits themselves, plus one more cycle for the start/reset (and, in most datasheets, the transfer of the result to the output latch).
The clock period first :
\(T=\dfrac{1}{f}=\dfrac{1}{1\times10^{6}}=1\ \mu\text{s}\)
Then the conversion time :
\(t_{conv}=(n+1)\,T=(8+1)(1\ \mu\text{s})=9\ \mu\text{s}\)
which is option 3.
Why the extra cycle appears. The bare bit-trial count is 8, giving 8 μs, and that figure is not among the options — the examiner is using the convention, common in Indian textbooks and in most real datasheets, that the conversion also consumes one housekeeping cycle at the start. Both conventions appear in the literature, so quote whichever the question's numbers support; here only \((n+1)T\) lands on an offered value. The answer is therefore flagged for confirmation against the official key.
The defining property of the SAR converter is that its conversion time is fixed, independent of the input voltage. Compare the alternatives:
| Type | Conversion time | Speed |
|---|---|---|
| Flash | 1 clock — parallel comparators | Fastest, but needs \(2^{n}-1\) comparators |
| Successive approximation | n clocks, fixed | Medium — the workhorse |
| Counter / ramp | Up to \(2^{n}\) clocks, input dependent | Slow |
| Dual slope | \(2^{n+1}\) clocks | Slowest, but excellent noise rejection |
For the same 8 bits and 1 MHz clock, a counter-type converter would take up to 256 μs and a dual-slope one over 500 μs, which is exactly why the SAR dominates data-acquisition front ends where a predictable sampling interval matters.
Hence, the conversion time is 9 μs.
Similar Questions
In successive approximation converter input to the comparator is through
Assertion (A) : Dual slope (A/D) converter is the most preferred conversion technique employed in most of the digital multimeters.
Reason (R) : Dual slope (A/D) converter provides high accuracy while at the same time suppresses the HUM effect on the input signal.
Assertion (A) : Dual-slope A/D converter is most preferred A/D conversion approach in digital multimeters.
Reason (R) : Dual-slope A/D converter provides high accuracy in A/D conversion, while at the same time suppressing the hum effect on the input signal.
A dual slope A to D converter has the following :
(a) a differentiator
(b) a comparator
(c) an integrator
(d) a binary counter
Out of above, following is correct :
For A to D converters, following statements are given :
(a) It is the process of converting time varying input to discrete output levels.
(b) Flash type A/D conversion are slow in nature.
(c) The quantisation error depends upon the step size of quantisation.
(d) Flash type A/D conversion is a simultaneous conversion.
Which of the above are correct ?
Assertion (A) : The output of an 8 bit A to D convertor is 80H for an input of 2.5V.
Reason (R) : ADC has an output range of 00 to FFH for an input range of −5V to +5V.
Select your answer using the codes given below.
Which of the following A/D convertor is fastest ?
An analog voltage in the range 0 to V volts is to be converted into 3 bit digital output. It is divided into eight intervals. The top and bottom intervals are \(\dfrac{V}{14}\) and the middle six intervals are \(\dfrac{V}{7}\). The maximum quantization error will be :
List – I List – II a. Flash converter i. Integrating type b. Successive approximation ii. Fastest converter c. Counter Ramp iii. Maximum conversion Time = N bits d. Dual Slope iv. Uses a DAC in its feedback patd Codes :
Important Questions from Analog To Digital Converters
Which is known as flash converter?
A 200 mV full-scale dual-slope analog to digital converter (DS-ADC) has a reference voltage of 100 mV. The first integration time is set as 100 ms. The DS-ADC is operated in the continuous conversion mode. The conversion time of the DS-ADC for an input voltage of 123.4 mV (in ms, rounded off to one decimal place) is
- The minimum number of comparators required in a 6-bit flash analog-to-digital converter is ________. (answer in integer)
- The number of comparator required for a 5 bit flash ADC is ____________.
In successive approximation converter input to the comparator is through
