A dual slope A to D converter has the following : (a) a differentiator (b) a comparator (c) an integrator (d) a binary counter Out of above, following is correct :
(c), (b), (d)
How a dual-slope converter works — the block list follows directly from the two phases of its operation.
Phase 1 (run-up). The unknown input is applied to an integrator for a fixed time T1, counted out by a binary counter. The integrator output ramps to
\(V_1=-\dfrac{V_{in}T_1}{RC}\)
so the height reached is proportional to the input.
Phase 2 (run-down). The input is switched to a reference of opposite polarity and the integrator ramps back towards zero at a fixed slope. The comparator watches for the zero crossing and stops the counter. The measured time T2 gives
\(V_{in}=V_{ref}\dfrac{T_2}{T_1}\)
and the count held in the counter is the digital output.
So the three essential blocks are the integrator (c), the comparator (b) and the binary counter (d) — option 3. There is no differentiator anywhere in the architecture; a differentiator would amplify noise, which is the exact opposite of what this converter is designed for.
Why the "dual slope" trick is so good. Look at the final equation: R, C and the clock frequency have cancelled out. Both phases use the same integrator and the same clock, so drift in the components, the clock or the supply affects both ramps equally and divides away. That gives excellent accuracy and stability without precision parts.
Better still, integrating the input over a fixed window averages out noise; choosing \(T_1\) as an exact multiple of the mains period nulls 50 Hz interference completely. The price is speed — a conversion takes thousands of clock cycles — which is why dual-slope converters are used in digital multimeters and panel meters rather than in fast data acquisition, where successive-approximation or flash converters are used instead.
Hence, the correct answer is (c), (b), (d).
Similar Questions
In successive approximation converter input to the comparator is through
Assertion (A) : Dual slope (A/D) converter is the most preferred conversion technique employed in most of the digital multimeters.
Reason (R) : Dual slope (A/D) converter provides high accuracy while at the same time suppresses the HUM effect on the input signal.
Assertion (A) : Dual-slope A/D converter is most preferred A/D conversion approach in digital multimeters.
Reason (R) : Dual-slope A/D converter provides high accuracy in A/D conversion, while at the same time suppressing the hum effect on the input signal.
For A to D converters, following statements are given :
(a) It is the process of converting time varying input to discrete output levels.
(b) Flash type A/D conversion are slow in nature.
(c) The quantisation error depends upon the step size of quantisation.
(d) Flash type A/D conversion is a simultaneous conversion.
Which of the above are correct ?
Assertion (A) : The output of an 8 bit A to D convertor is 80H for an input of 2.5V.
Reason (R) : ADC has an output range of 00 to FFH for an input range of −5V to +5V.
Select your answer using the codes given below.
Which of the following A/D convertor is fastest ?
The conversion time for an 8-bit successive approximation ADC which is driven by 1-MHz clock is :
An analog voltage in the range 0 to V volts is to be converted into 3 bit digital output. It is divided into eight intervals. The top and bottom intervals are \(\dfrac{V}{14}\) and the middle six intervals are \(\dfrac{V}{7}\). The maximum quantization error will be :
List – I List – II a. Flash converter i. Integrating type b. Successive approximation ii. Fastest converter c. Counter Ramp iii. Maximum conversion Time = N bits d. Dual Slope iv. Uses a DAC in its feedback patd Codes :
Important Questions from Analog To Digital Converters
Which is known as flash converter?
A 200 mV full-scale dual-slope analog to digital converter (DS-ADC) has a reference voltage of 100 mV. The first integration time is set as 100 ms. The DS-ADC is operated in the continuous conversion mode. The conversion time of the DS-ADC for an input voltage of 123.4 mV (in ms, rounded off to one decimal place) is
- The minimum number of comparators required in a 6-bit flash analog-to-digital converter is ________. (answer in integer)
- The number of comparator required for a 5 bit flash ADC is ____________.
In successive approximation converter input to the comparator is through
