An analog voltage in the range 0 to V volts is to be converted into 3 bit digital output. It is divided into eight intervals. The top and bottom intervals are \(\dfrac{V}{14}\) and the middle six intervals are \(\dfrac{V}{7}\). The maximum quantization error will be :
\(\dfrac{V}{14}\)
Quantization error is the difference between the actual input and the level the converter reports. If each code represents the centre of its interval, the worst error occurs at either edge of the interval and equals half its width:
\(e_{max}=\dfrac{\Delta}{2}\)
First check that the intervals add up.
\(2\times\dfrac{V}{14}+6\times\dfrac{V}{7}=\dfrac{V}{7}+\dfrac{6V}{7}=V\ \checkmark\)
so the eight intervals do span the full range.
Now take the largest interval, which is one of the six middle ones of width V/7:
\(e_{max}=\dfrac{1}{2}\times\dfrac{V}{7}=\dfrac{V}{14}\)
which is option 3.
Why the end intervals were made half-width — this is the whole design idea. The two extreme intervals have their code at the edge of the range (0 and V) rather than at a centre, so an error of half a full interval is impossible there; making them V/14 wide gives them a maximum error of exactly V/14 as well. Every interval in the converter therefore contributes the same worst-case error:
| Interval | Width | Code placed at | Max error |
|---|---|---|---|
| Bottom | V/14 | Edge (0) | V/14 |
| Middle six | V/7 | Centre | V/14 |
| Top | V/14 | Edge (V) | V/14 |
This is precisely the mid-tread arrangement used in real converters, and it is why a datasheet quotes \(\pm\tfrac{1}{2}\) LSB rather than \(\pm1\) LSB.
Compare with the naive uniform design. Eight equal intervals of V/8 with codes at the interval boundaries would give a maximum error of V/8 at some points — worse than V/14 — and the error would not be symmetric about zero. Splitting the end steps buys a uniform, symmetric error at no extra hardware cost.
The general result for an n-bit converter of full scale V is
\(e_{max}=\dfrac{V}{2\left(2^{n}-1\right)}\)
and with n = 3 this gives \(\dfrac{V}{2\times7}=\dfrac{V}{14}\), confirming the answer. Quantization noise power is then \(\Delta^{2}/12\), giving the familiar 6 dB of signal-to-noise ratio per bit.
Hence, the maximum quantization error is V/14.
Similar Questions
In successive approximation converter input to the comparator is through
Assertion (A) : Dual slope (A/D) converter is the most preferred conversion technique employed in most of the digital multimeters.
Reason (R) : Dual slope (A/D) converter provides high accuracy while at the same time suppresses the HUM effect on the input signal.
Assertion (A) : Dual-slope A/D converter is most preferred A/D conversion approach in digital multimeters.
Reason (R) : Dual-slope A/D converter provides high accuracy in A/D conversion, while at the same time suppressing the hum effect on the input signal.
A dual slope A to D converter has the following :
(a) a differentiator
(b) a comparator
(c) an integrator
(d) a binary counter
Out of above, following is correct :
For A to D converters, following statements are given :
(a) It is the process of converting time varying input to discrete output levels.
(b) Flash type A/D conversion are slow in nature.
(c) The quantisation error depends upon the step size of quantisation.
(d) Flash type A/D conversion is a simultaneous conversion.
Which of the above are correct ?
Assertion (A) : The output of an 8 bit A to D convertor is 80H for an input of 2.5V.
Reason (R) : ADC has an output range of 00 to FFH for an input range of −5V to +5V.
Select your answer using the codes given below.
Which of the following A/D convertor is fastest ?
The conversion time for an 8-bit successive approximation ADC which is driven by 1-MHz clock is :
List – I List – II a. Flash converter i. Integrating type b. Successive approximation ii. Fastest converter c. Counter Ramp iii. Maximum conversion Time = N bits d. Dual Slope iv. Uses a DAC in its feedback patd Codes :
Important Questions from Analog To Digital Converters
Which is known as flash converter?
A 200 mV full-scale dual-slope analog to digital converter (DS-ADC) has a reference voltage of 100 mV. The first integration time is set as 100 ms. The DS-ADC is operated in the continuous conversion mode. The conversion time of the DS-ADC for an input voltage of 123.4 mV (in ms, rounded off to one decimal place) is
- The minimum number of comparators required in a 6-bit flash analog-to-digital converter is ________. (answer in integer)
- The number of comparator required for a 5 bit flash ADC is ____________.
In successive approximation converter input to the comparator is through
