In successive approximation converter input to the comparator is through
DAC
A successive-approximation ADC works by guessing a code and checking it, and the checking requires the guess to be turned back into a voltage — which is what the internal DAC does — option 1.
The loop, one step at a time.
| Step | Block | Action |
|---|---|---|
| 1 | SAR | Sets a trial code, starting with the MSB |
| 2 | DAC | Converts that code to an analogue voltage |
| 3 | Comparator | Compares it with the input |
| 4 | SAR | Keeps or clears the bit, moves to the next |
The comparator has two inputs: the unknown analogue signal on one, and the DAC's output on the other. It is the second of these that the question asks about.
Why the search is fast. Each comparison resolves exactly one bit, halving the remaining uncertainty — a binary search. An n-bit conversion therefore needs n clock periods, against \(2^{n}\) for a counter-type converter:
\(t_{conv}=n\,T_{clk}\)
Twelve bits take twelve clocks rather than 4096, which is why the successive-approximation architecture dominates the medium-speed, medium-resolution range.
Why option 4 is the thoughtful wrong answer. A sample-and-hold is present in a practical SAR converter, and for a good reason: the input must not move during the conversion, or early bit decisions would be made against a different value from later ones. But the sample-and-hold sits in the signal path, feeding the comparator's other input; it is not what closes the feedback loop. The question asks what the trial value comes through, and that is the DAC.
Options 2 and 3 are components, not stages. Latches and flip-flops make up the successive-approximation register itself — they store the code being assembled — but they hold digital values and cannot present anything to a comparator that compares voltages.
The consequence for accuracy follows from the same structure: the converter can be no more accurate than its internal DAC, since every decision is a comparison against a DAC output. An n-bit SAR ADC needs an n-bit-accurate DAC, and that is what usually limits the design.
Hence, the comparator's input comes through the DAC.
Similar Questions
Assertion (A) : Dual slope (A/D) converter is the most preferred conversion technique employed in most of the digital multimeters.
Reason (R) : Dual slope (A/D) converter provides high accuracy while at the same time suppresses the HUM effect on the input signal.
Assertion (A) : Dual-slope A/D converter is most preferred A/D conversion approach in digital multimeters.
Reason (R) : Dual-slope A/D converter provides high accuracy in A/D conversion, while at the same time suppressing the hum effect on the input signal.
A dual slope A to D converter has the following :
(a) a differentiator
(b) a comparator
(c) an integrator
(d) a binary counter
Out of above, following is correct :
For A to D converters, following statements are given :
(a) It is the process of converting time varying input to discrete output levels.
(b) Flash type A/D conversion are slow in nature.
(c) The quantisation error depends upon the step size of quantisation.
(d) Flash type A/D conversion is a simultaneous conversion.
Which of the above are correct ?
Assertion (A) : The output of an 8 bit A to D convertor is 80H for an input of 2.5V.
Reason (R) : ADC has an output range of 00 to FFH for an input range of −5V to +5V.
Select your answer using the codes given below.
Which of the following A/D convertor is fastest ?
The conversion time for an 8-bit successive approximation ADC which is driven by 1-MHz clock is :
An analog voltage in the range 0 to V volts is to be converted into 3 bit digital output. It is divided into eight intervals. The top and bottom intervals are \(\dfrac{V}{14}\) and the middle six intervals are \(\dfrac{V}{7}\). The maximum quantization error will be :
List – I List – II a. Flash converter i. Integrating type b. Successive approximation ii. Fastest converter c. Counter Ramp iii. Maximum conversion Time = N bits d. Dual Slope iv. Uses a DAC in its feedback patd Codes :
Important Questions from Analog To Digital Converters
Which is known as flash converter?
A 200 mV full-scale dual-slope analog to digital converter (DS-ADC) has a reference voltage of 100 mV. The first integration time is set as 100 ms. The DS-ADC is operated in the continuous conversion mode. The conversion time of the DS-ADC for an input voltage of 123.4 mV (in ms, rounded off to one decimal place) is
- The minimum number of comparators required in a 6-bit flash analog-to-digital converter is ________. (answer in integer)
- The number of comparator required for a 5 bit flash ADC is ____________.
Assertion (A) : Dual slope (A/D) converter is the most preferred conversion technique employed in most of the digital multimeters.
Reason (R) : Dual slope (A/D) converter provides high accuracy while at the same time suppresses the HUM effect on the input signal.
