Codes :List – I List – II a. Flash converter i. Integrating type b. Successive approximation ii. Fastest converter c. Counter Ramp iii. Maximum conversion Time = N bits d. Dual Slope iv. Uses a DAC in its feedback patd
a-ii, b-iii, c-iv, d-i
a-ii, b-iii, c-iv, d-i — option (A).
| Converter | Matches | Why |
|---|---|---|
| a. Flash | ii. Fastest converter | Uses \(2^{N}-1\) comparators, all firing at once against a resistor-ladder reference, so the conversion is complete in one clock period. The price is exponential hardware — an 8-bit flash needs 255 comparators — which is why flash is confined to low resolution and very high speed |
| b. Successive approximation | iii. Maximum conversion time = N bits | The SAR tests one bit per clock, starting at the MSB, so an N-bit conversion takes exactly N clock periods — and the time is fixed, independent of the input value |
| c. Counter ramp | iv. Uses a DAC in its feedback path | A counter drives a DAC whose output ramps upward until a comparator says it has passed the input. Conversion time is proportional to the input and can reach \(2^{N}\) clocks in the worst case |
| d. Dual slope | i. Integrating type | Integrates the input for a fixed time, then de-integrates a reference until the integrator returns to zero. Slow, but the component values cancel out |
The one pairing that decides the question. Both the SAR and the counter-ramp converter contain a DAC in a feedback loop, so item (iv) on its own does not separate them. What does separate them is item (iii):
| Successive approximation | Counter ramp | |
|---|---|---|
| Clocks per conversion | N, always | Up to \(2^{N}\), and input-dependent |
| Search strategy | Binary search — halve the range each step | Linear count from zero |
“Maximum conversion time = N bits” can only be the SAR, because the counter ramp’s maximum is \(2^{N}\), not N. Fixing b-iii forces c-iv, and the matching closes.
Why dual slope survives in instruments. Its accuracy does not depend on the integrating capacitor or resistor, because the same components are used in both phases and cancel:
\(V_{in}=V_{ref}\dfrac{t_{2}}{t_{1}}\)
Choosing the integration period as an exact multiple of the mains period also rejects 50 Hz hum. That combination — component-independent accuracy plus noise rejection — is why digital multimeters use dual slope despite its being the slowest type in the list.
The overall trade-off, from fastest to slowest: flash, SAR, counter ramp, dual slope, with hardware cost and power running in the opposite direction.
Hence, the matching is a-ii, b-iii, c-iv, d-i.
Similar Questions
In successive approximation converter input to the comparator is through
Assertion (A) : Dual slope (A/D) converter is the most preferred conversion technique employed in most of the digital multimeters.
Reason (R) : Dual slope (A/D) converter provides high accuracy while at the same time suppresses the HUM effect on the input signal.
Assertion (A) : Dual-slope A/D converter is most preferred A/D conversion approach in digital multimeters.
Reason (R) : Dual-slope A/D converter provides high accuracy in A/D conversion, while at the same time suppressing the hum effect on the input signal.
A dual slope A to D converter has the following :
(a) a differentiator
(b) a comparator
(c) an integrator
(d) a binary counter
Out of above, following is correct :
For A to D converters, following statements are given :
(a) It is the process of converting time varying input to discrete output levels.
(b) Flash type A/D conversion are slow in nature.
(c) The quantisation error depends upon the step size of quantisation.
(d) Flash type A/D conversion is a simultaneous conversion.
Which of the above are correct ?
Assertion (A) : The output of an 8 bit A to D convertor is 80H for an input of 2.5V.
Reason (R) : ADC has an output range of 00 to FFH for an input range of −5V to +5V.
Select your answer using the codes given below.
Which of the following A/D convertor is fastest ?
The conversion time for an 8-bit successive approximation ADC which is driven by 1-MHz clock is :
An analog voltage in the range 0 to V volts is to be converted into 3 bit digital output. It is divided into eight intervals. The top and bottom intervals are \(\dfrac{V}{14}\) and the middle six intervals are \(\dfrac{V}{7}\). The maximum quantization error will be :
Important Questions from Analog To Digital Converters
Which is known as flash converter?
A 200 mV full-scale dual-slope analog to digital converter (DS-ADC) has a reference voltage of 100 mV. The first integration time is set as 100 ms. The DS-ADC is operated in the continuous conversion mode. The conversion time of the DS-ADC for an input voltage of 123.4 mV (in ms, rounded off to one decimal place) is
- The minimum number of comparators required in a 6-bit flash analog-to-digital converter is ________. (answer in integer)
- The number of comparator required for a 5 bit flash ADC is ____________.
In successive approximation converter input to the comparator is through
