Match List I with List II Choose the correct answer from the options given below:LIST I (Diagram) LIST II (Sequential Circuit) A. 
I. Edge triggered S-R flip flop B. 
II. D Flip flop to SR flip flop C. 
III. Gated Latch clocked flip flop D. 
IV. Gated D Latch
A-III, B-IV, C-I, D-II
How to identify each sequential circuit from its diagram. Look at three things: what the data inputs are (S and R, or a single D), how the clock/enable line is applied (level-sensitive gating versus an edge-detecting front end), and whether extra gates convert one flip-flop type into another.
A → III, gated (clocked) S-R latch. The diagram shows the S and R inputs entering a pair of steering NAND gates that are enabled by the clock line, feeding a cross-coupled NAND pair. The latch responds to S and R only while the clock level is asserted — a level-sensitive (gated) clocked latch, not an edge-triggered device.
B → IV, gated D latch. Here there is a single data input D, which is split into two paths — D and its inverted form — and applied through an enable (EN) line to an S-R style latch. Producing R as the complement of S is exactly what removes the forbidden S = R = 1 state and makes Q follow D whenever EN is high (transparent), holding the last value when EN goes low.
C → I, edge-triggered S-R flip-flop. This diagram adds a pulse/edge-detecting front end (a narrow-pulse network on the CLK path) ahead of the steering gates, so the S and R inputs are sampled only at the clock transition rather than throughout the clock level. Edge triggering is what prevents the output from following input changes during the whole clock pulse.
D → II, D flip-flop converted to an S-R flip-flop. The S and R signals pass through combinational gates that compute the required D excitation before entering a D-Q block. The conversion uses the S-R characteristic equation
\(D=Q_{n+1}=S+\overline{R}Q_n\)
which is the standard flip-flop-conversion procedure: write the target flip-flop's next-state equation, then realise it as the D input.
Key distinction being tested: a latch is level-sensitive (transparent while enabled) whereas a flip-flop is edge-triggered (samples only at a clock edge) — the gating structure in the diagram is what tells the two apart.
Hence, the correct matching is A-III, B-IV, C-I, D-II.
Similar Questions
The truth table of D flip-flop is given below:
C D Qn+1 O X Qn (Last State) $\uparrow$ 0 0 $\uparrow$ 1 1 Choose exact characteristic equation based on above Truth Table
Assertion (A) : Delay flip flop is used to store a single bit either 0 or 1.
Reason (R) : It has only one input, when clock is high and D input is also high, the output resets.
Assertion (A) : Asynchronous sequential circuit is also called event driven circuit.
Reason (R) : Event driven circuit does not have clock to trigger change of state. The states are changed by the change in input signal of the previous stage.
Select your answer using the codes given below.
For the circuit shown below consider the two statements :
Assertion (A) : The circuit is sequential.
Reason (R) : There is a loop in circuit.
Select your answer using the codes given below.
Flip Flop can be used to make :
(a) Latches
(b) Bounce-elimination switches
(c) ADDER
(d) Encoder
Which of the statements given above are correct ?
Under which input condition, the J-K Flip-Flop toggles ?
Read the following statements :
(a) In a J-K Flip Flop, if J = K, the resulting Flip Flop is referred to as a T-type Flip Flop
(b) In a J-K Flip Flop, if J ≠ K, the resulting Flip Flop is referred to as a D-type Flip Flop
(c) An S-R Flip Flop cannot be converted into a T-type Flip Flop since S = R = 1 is not allowed.Which is correct ?
Which of the following statements are true regarding the operation of JK flip-flop ?
1. When K input is low and J input is high, the Q output of the flip flop is reset.
2. When K input is high and J input is low, the output Q of the flip flop is set.
3. When both the inputs K and J are low, the output Q does not change.
4. When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on next positive clock edge.Which one of the following is true ?
Assertion (A) : D-flip-flops are used as buffer register.
Reason (R) : Flip-flops are free from "race-around" condition.
Select your answer using the codes given below :
In the circuit shown below, the output Y1 and Y2 for the given initial condition Y1 = Y2 = 1 and after four input pulses will be
Important Questions from Sequential Circuits
A basic memory storage element in a digital system is:
The basic sequential logic building block in which the output follows the data input as long as the ENABLE input is active, is
What can be the maximum clock frequency of a 10-bit ripple counter which will not cause a count to skip, considering 10 ns propagation delay for each of the edge-triggered flip flops?
The output of a sequential circuit depends on
The basic building block of a sequential logic circuit is
