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Question

In MOS

A. The substrate fermi potential ϕF is negative in NMOS

B. The substrate fermi potential ϕF is positive in NMOS

C. The substrate bias voltage VSB is positive in NMOS, negative in PMOS

D. The substrate bias voltage VSB is negative in NMOS, positive in PMOS.

Choose the correct answer from the options given below:

This question was previously asked in
UGC NET 2023 Home Science Question Paper (13-Dec-2023) (Shift 1)
The correct answer is

A & C only

 To solve this question, let's examine the statements about the Metal-Oxide-Semiconductor (MOS) structure, specifically concerning NMOS transistors.

  1. Explanation of Substrate Fermi Potential (φF):
    • In semiconductor physics, the Fermi potential (φF) is determined by the doping level of the substrate. For an NMOS (n-channel MOS), the substrate is typically a p-type semiconductor.
    • For a p-type substrate, the Fermi level is below the intrinsic Fermi level, meaning that φF is indeed negative. Thus, statement A is correct.
  2. Explanation of Substrate Bias Voltage (VSB):
    • The substrate bias voltage (VSB) is the voltage difference between the source and the substrate. In an NMOS, the source is typically connected to the ground or a lower potential, while the substrate is at a higher potential, resulting in a positive VSB.
    • Conversely, in a PMOS (p-channel MOS), the substrate is typically n-type. The source is at a higher potential, and the substrate at a lower potential, making VSB negative.
    • Thus, statement C correctly describes the scenario for NMOS and PMOS, making it a correct statement.
  3. Elimination of Incorrect Options:
    • Statement B, which states that the substrate Fermi potential (φF) is positive in NMOS, is incorrect since we established it is negative for a p-type substrate.
    • Statement D, which states that VSB is negative in NMOS and positive in PMOS, contradicts the explanation provided in step 2 regarding substrate bias conditions.

Based on the explanations above, the correct answer is: A & C only.

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Similar Questions

  1. In enhancement mode MOSFET the saturation (drain) current is given by

    (a) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}\)

    (b) \(K\dfrac{W}{L}(V_{gs}-V_{th})(1+\lambda V_{ds})\)

    (c) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}(1+\lambda V_{ds})\)

    (d) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}(1-\lambda V_{ds})\)

    Out of these

  2. For an n-channel MOS transistor with $\mu_n$ = 600 cm2/Vs, Cox = 7 x 10-8  F/cm2, W = 40 $\mu_m$, L = 4$\mu_m$ and VTO=1.0 V, the value of K parameter is:

  3. Approximate oxide capacitance value (Cgd) for saturation operating mode of MOS transistor is:

  4. In a MOSFET the drain saturation current is

  5. The threshold voltage of a MOSFET can be lowered by

    1. using a thinner gate oxide
    2. reducing the carrier concentration in the substrate
    3. increasing the carrier concentration in the substrate

    Of these statements :

  6. The threshold voltage of an n-channel MOSFET can be increased by

  7. The threshold voltage of an n-channel MOSFET can be increased by

  8. Assertion (A) : MOS ICs based on MOSFET structure find wide applications in digital field.

    Reason (R) : MOS ICs have small size and are easy to fabricate.

  9. In MOSFET, the carrier velocity between constant mobility regime and the saturation velocity can be described as :

  10. In MOSFET, the linear region current is :

    (A) \(\dfrac{\mu_{n}C_{ox}w}{L}\left(V_{gs}-V_{th}-\dfrac{V_{ds}}{2}\right)V_{ds}\)
    (B) \(\dfrac{\mu_{n}C_{ox}w}{L}\left(V_{gs}-V_{th}\right)V_{ds}\)
    (C) \(\dfrac{\mu_{n}C_{ox}w}{2L}\left(V_{gs}-V_{th}\right)V_{ds}^{2}\)
    (D) \(\dfrac{\mu_{n}C_{ox}w}{L}\left(V_{gs}-V_{th}\right)^{2}\)

    Choose the most appropriate answer from the options given below :


Important Questions from MOSFET

  1. Which industry does aluminium smelting belong to?

  2. Given, Vgs is the gate-source voltage, Vds is the drain source voltage, and Vth is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are

  3. A switched mode power supply operating at 20 kHz to 100 kHz range uses as the main switching element is __________.

  4. Which semiconductor power device out of the following, is not a current triggering device?

  5. A CMOS amplifier when compared to an N–channel MOSFET, has the advantage of

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