In enhancement mode MOSFET the saturation (drain) current is given by (a) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}\) (b) \(K\dfrac{W}{L}(V_{gs}-V_{th})(1+\lambda V_{ds})\) (c) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}(1+\lambda V_{ds})\) (d) \(K\dfrac{W}{L}(V_{gs}-V_{th})^{2}(1-\lambda V_{ds})\) Out of these
(a) and (c) are correct.
The basic saturation law. Beyond pinch-off the drain current of an enhancement MOSFET depends on the gate overdrive squared and is nearly independent of Vds:
\(I_D=K\dfrac{W}{L}(V_{gs}-V_{th})^{2}\)
That is statement (a), the first-order (long-channel) model.
Adding channel-length modulation. In a real device, raising Vds pushes the pinch-off point back towards the source, shortening the effective channel by ΔL. Since \(I_D\propto1/L_{eff}\), the current creeps up slightly with Vds, giving the saturation characteristic a small positive slope. The effect is modelled by one extra factor:
\(I_D=K\dfrac{W}{L}(V_{gs}-V_{th})^{2}(1+\lambda V_{ds})\)
which is statement (c). So (a) and (c) are the two correct forms — the same law without and with the second-order correction.
Why the other two fail.
Statement (b) loses the square on the overdrive. A linear dependence would describe the triode region, not saturation, and it would wreck the quadratic transfer characteristic that gives the MOSFET its constant transconductance slope \(g_m=2\sqrt{K\frac{W}{L}I_D}\).
Statement (d) has \((1-\lambda V_{ds})\), the wrong sign. That would make the current fall as Vds rises, i.e. a negative output resistance — the opposite of what is observed.
What λ means in practice. It is the reciprocal of the Early-like voltage and sets the output resistance of the device:
\(r_o=\dfrac{1}{\lambda I_D}\)
which is exactly what limits the intrinsic gain \(g_mr_o\) of an amplifier stage. Short-channel devices have larger λ, which is why analog designers deliberately use longer channels where high gain is needed.
Hence, the correct expressions are (a) and (c).
Similar Questions
The threshold voltage of an n-channel MOSFET can be increased by
Assertion (A) : MOS ICs based on MOSFET structure find wide applications in digital field.
Reason (R) : MOS ICs have small size and are easy to fabricate.
In MOSFET, the linear region current is :
(A) \(\dfrac{\mu_{n}C_{ox}w}{L}\left(V_{gs}-V_{th}-\dfrac{V_{ds}}{2}\right)V_{ds}\)
(B) \(\dfrac{\mu_{n}C_{ox}w}{L}\left(V_{gs}-V_{th}\right)V_{ds}\)
(C) \(\dfrac{\mu_{n}C_{ox}w}{2L}\left(V_{gs}-V_{th}\right)V_{ds}^{2}\)
(D) \(\dfrac{\mu_{n}C_{ox}w}{L}\left(V_{gs}-V_{th}\right)^{2}\)Choose the most appropriate answer from the options given below :
Approximate oxide capacitance value (Cgd) for saturation operating mode of MOS transistor is:
For an n-channel MOS transistor with $\mu_n$ = 600 cm2/Vs, Cox = 7 x 10-8 F/cm2, W = 40 $\mu_m$, L = 4$\mu_m$ and VTO=1.0 V, the value of K parameter is:
In MOS
A. The substrate fermi potential ϕF is negative in NMOS
B. The substrate fermi potential ϕF is positive in NMOS
C. The substrate bias voltage VSB is positive in NMOS, negative in PMOS
D. The substrate bias voltage VSB is negative in NMOS, positive in PMOS.
Choose the correct answer from the options given below:
In a MOSFET the drain saturation current is
For the n-channel MOSFET shown in the figure given below, threshold voltage Vth = 2 V. The drain current ID of the MOSFET is 4 mA when the drain resistance RD is 1 kΩ. If the value of RD is increased to 4 kΩ, then the drain current ID will become :
The threshold voltage of a MOSFET can be lowered by
1. using a thinner gate oxide
2. reducing the carrier concentration in the substrate
3. increasing the carrier concentration in the substrateOf these statements :
The threshold voltage of an n-channel MOSFET can be increased by
Important Questions from MOSFET
An n-channel MOSFET is connected as shown in the Figure.
Assume $V_{TH} = 1\text{ V}$, $V_{DD} = 5\text{ V}$, and $\mu C_{ox}\left(\frac{W}{L}\right) = 2\text{ mA V}^{-2}$ and neglect channel length modulation effects.
The gate voltage ($V_G$) of the n-channel MOSFET (in Volt) is __.
(rounded off to two decimal places)
- A semiconductor uses P-type substrates with $N_A = 5 \times 10^{15}cm^{-3}$ in an n-MOS device having depletion region width of 0.415 $\mu$m. What is the depletion charge in magnitude?
- MOSFETs exhibit a non-linear relationship between input voltage and output current due to the device construction. The non-linear relationship is connected through the device parameter 'K'. Calculate 'K' for a specific MOSFET operating with an input voltage of 6 V and output current of 10 mA. The Threshold voltage of the chosen MOSFET is 4 V.
- Given below are two statements: one is labelled as Assertion (a) and the other is labelled as Reason (r).
Assertion (a): In a ratioless logic, the transistors can be of minimum size.
Reason (r): In a ratioless logic, the logic levels are not dependent upon the relative device size. - What are the effects of increasing temperature in the I-V characteristics of the NMOS transistor ?
