In a J-K FF, if J = Q and K = 1 (see figure). Assuming the flip flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be :
010101
Work out what the flip-flop does in each of its two possible states, and the pattern follows immediately.
The J-K rule is: J = K = 1 toggles, J = 0 with K = 1 resets, J = 1 with K = 0 sets, J = K = 0 holds. Here K is permanently 1 and J follows \(\overline{Q}\), so only two cases arise:
| Present Q | J = Q | K | Action | Next Q |
|---|---|---|---|---|
| 0 | 1 | 1 | Toggle | 1 |
| 1 | 0 | 1 | Reset | 0 |
Both rows produce a change of state, by different routes: from 0 the flip-flop toggles to 1, and from 1 it is reset back to 0. The output therefore alternates on every clock edge, exactly as a plain toggle flip-flop would — the arrangement is a divide-by-two.
Reading off the sequence. The flip-flop starts cleared, so Q = 0, and the output then alternates:
\(0\rightarrow1\rightarrow0\rightarrow1\rightarrow0\rightarrow1\)
Sampling the Q output at six successive points beginning from the cleared state gives 010101 — option 4.
Why the other options are impossible. Every one of them contains two adjacent equal bits — 010000 has four zeros in a row, 011001 has a repeated 1 and a repeated 0, 010010 has two adjacent zeros. But the table above shows the output cannot stay put: whatever state it is in, the next clock changes it. Only an alternating pattern is possible, and option 4 is the only alternating sequence offered. That check alone settles the question without tracing a single pulse.
Why the feedback is redundant here. Tying J to \(\overline{Q}\) looks as though it should do something clever, but the two rows collapse to the same behaviour as simply tying J to 1. The circuit is a T flip-flop in disguise, and its output frequency is half the clock frequency — the building block of every binary counter.
One practical caution : feeding an output back to an input of the same flip-flop is safe only with an edge-triggered or master-slave device. A level-triggered latch would race around while the clock stayed high, toggling repeatedly and ending in an unpredictable state.
Hence, the sequence at Q is 010101.
Similar Questions
The truth table of D flip-flop is given below:
C D Qn+1 O X Qn (Last State) $\uparrow$ 0 0 $\uparrow$ 1 1 Choose exact characteristic equation based on above Truth Table
Assertion (A) : Delay flip flop is used to store a single bit either 0 or 1.
Reason (R) : It has only one input, when clock is high and D input is also high, the output resets.
Assertion (A) : Asynchronous sequential circuit is also called event driven circuit.
Reason (R) : Event driven circuit does not have clock to trigger change of state. The states are changed by the change in input signal of the previous stage.
Select your answer using the codes given below.
For the circuit shown below consider the two statements :
Assertion (A) : The circuit is sequential.
Reason (R) : There is a loop in circuit.
Select your answer using the codes given below.
Flip Flop can be used to make :
(a) Latches
(b) Bounce-elimination switches
(c) ADDER
(d) Encoder
Which of the statements given above are correct ?
Under which input condition, the J-K Flip-Flop toggles ?
Read the following statements :
(a) In a J-K Flip Flop, if J = K, the resulting Flip Flop is referred to as a T-type Flip Flop
(b) In a J-K Flip Flop, if J ≠ K, the resulting Flip Flop is referred to as a D-type Flip Flop
(c) An S-R Flip Flop cannot be converted into a T-type Flip Flop since S = R = 1 is not allowed.Which is correct ?
Which of the following statements are true regarding the operation of JK flip-flop ?
1. When K input is low and J input is high, the Q output of the flip flop is reset.
2. When K input is high and J input is low, the output Q of the flip flop is set.
3. When both the inputs K and J are low, the output Q does not change.
4. When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on next positive clock edge.Which one of the following is true ?
Assertion (A) : D-flip-flops are used as buffer register.
Reason (R) : Flip-flops are free from "race-around" condition.
Select your answer using the codes given below :
In the circuit shown below, the output Y1 and Y2 for the given initial condition Y1 = Y2 = 1 and after four input pulses will be
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