Consider the following statements regarding registers and latches : (A) Registers are made of edge triggered flip-flops whereas latches are made from level triggered flip flops Choose the most appropriate answer from the options given below :
(B) Registers are temporary storage devices whereas latches are not
(C) A latch employs cross coupled feed back connections
(D) A register stores a binary word whereas a latch does not
(A) and (C) Only
The genuine difference between the two is when they capture data, not whether they store it — so (A) and (C) are true and (B) and (D) are false. Option 2.
(A) — the real distinction.
| Latch | Register | |
|---|---|---|
| Triggering | Level sensitive | Edge triggered |
| While enabled | Transparent — output follows input | Opaque — samples only at the edge |
| Timing analysis | Harder — borrowing across boundaries | Straightforward |
A latch passes its input straight through for as long as its enable is asserted, and freezes only when the enable is removed. A register samples at one instant — the clock edge — and holds for the whole period, which is why synchronous design is built on registers.
(C) is correct and describes the underlying mechanism. Two gates cross-coupled — each one's output feeding the other's input — form a bistable with two self-sustaining states. That feedback loop is what storage is, and every flip-flop contains one at its core.
(B) and (D) are false for the same reason, and it is the reason the question exists. Both assert that a latch does not store, which contradicts (C) in the very same list: a cross-coupled loop is a storage element by definition. A latch holds its value indefinitely once its enable is removed, exactly as a register does. The two statements confuse when storage happens with whether it happens.
Why the confusion arises is that a register is usually a group of flip-flops holding a multi-bit word, while "latch" often refers to a single bit. But that is a matter of how many are used, not of capability — an 8-bit latch such as the 74LS373 stores a whole byte, and it is called a latch because it is level sensitive, not because it stores less.
Where each is preferred. Registers dominate synchronous logic because a single clock edge gives every element a well-defined sampling instant, making timing closure tractable. Latches are smaller and faster and permit time borrowing between pipeline stages, so they appear in high-performance custom designs and in bus interfaces — for instance holding the address off the 8085's multiplexed bus while ALE is high.
Hence, the correct statements are (A) and (C).
Similar Questions
The truth table of D flip-flop is given below:
C D Qn+1 O X Qn (Last State) $\uparrow$ 0 0 $\uparrow$ 1 1 Choose exact characteristic equation based on above Truth Table
Assertion (A) : Delay flip flop is used to store a single bit either 0 or 1.
Reason (R) : It has only one input, when clock is high and D input is also high, the output resets.
Assertion (A) : Asynchronous sequential circuit is also called event driven circuit.
Reason (R) : Event driven circuit does not have clock to trigger change of state. The states are changed by the change in input signal of the previous stage.
Select your answer using the codes given below.
For the circuit shown below consider the two statements :
Assertion (A) : The circuit is sequential.
Reason (R) : There is a loop in circuit.
Select your answer using the codes given below.
Flip Flop can be used to make :
(a) Latches
(b) Bounce-elimination switches
(c) ADDER
(d) Encoder
Which of the statements given above are correct ?
Under which input condition, the J-K Flip-Flop toggles ?
Read the following statements :
(a) In a J-K Flip Flop, if J = K, the resulting Flip Flop is referred to as a T-type Flip Flop
(b) In a J-K Flip Flop, if J ≠ K, the resulting Flip Flop is referred to as a D-type Flip Flop
(c) An S-R Flip Flop cannot be converted into a T-type Flip Flop since S = R = 1 is not allowed.Which is correct ?
Which of the following statements are true regarding the operation of JK flip-flop ?
1. When K input is low and J input is high, the Q output of the flip flop is reset.
2. When K input is high and J input is low, the output Q of the flip flop is set.
3. When both the inputs K and J are low, the output Q does not change.
4. When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output toggle on next positive clock edge.Which one of the following is true ?
Assertion (A) : D-flip-flops are used as buffer register.
Reason (R) : Flip-flops are free from "race-around" condition.
Select your answer using the codes given below :
In the circuit shown below, the output Y1 and Y2 for the given initial condition Y1 = Y2 = 1 and after four input pulses will be
Important Questions from Sequential Circuits
A basic memory storage element in a digital system is:
The basic sequential logic building block in which the output follows the data input as long as the ENABLE input is active, is
What can be the maximum clock frequency of a 10-bit ripple counter which will not cause a count to skip, considering 10 ns propagation delay for each of the edge-triggered flip flops?
The output of a sequential circuit depends on
The basic building block of a sequential logic circuit is
