In "JZ Next" instruction of 8051 microcontroller, which register's content is checked to see if it is zero?
A
What the instruction does. JZ stands for "Jump if Zero". In the 8051 instruction set it is a conditional relative branch, and the register it tests is fixed by the instruction itself — it is always the accumulator, register A.
Execution of JZ Next, step by step.
1. The CPU examines the current contents of A.
2. If A = 00H (all eight bits zero), the signed 8-bit relative offset is added to the program counter and control transfers to the label "Next".
3. If A ≠ 00H, the branch is not taken and execution simply falls through to the next instruction.
Important properties. JZ tests the accumulator without altering it, and — unlike JC/JNC, which test the carry flag — there is no zero flag in the 8051 PSW at all; the zero condition is evaluated on the fly from A. The branch is relative, so the target must lie within −128 to +127 bytes of the following instruction.
Why the other registers cannot be tested directly. There is no instruction that tests B, R1, R2 (or any other register or memory location) for zero. To test such a register you must first bring its value into the accumulator, for example:
\(\texttt{MOV A, R1}\ \rightarrow\ \texttt{JZ Next}\)
A common alternative when the register is a loop counter is DJNZ R1, Label, which decrements the register and branches while it is non-zero — that one does work on R0–R7 directly.
Companion instruction. JNZ ("jump if not zero") is the exact complement and likewise tests only A.
Hence, the register whose content is checked by the JZ instruction is the accumulator, A.
In an 8086, AL = 19 BCD & BL = 36 BCD prior to execution of following example
ADD AL, BL
DAA
What will be content of AL after execution of the example ?
If SS = 3000 H and SP = 2000 H in 8086 microprocessor, in which memory addresses the contents of BL and BH are stored respectively, when PUSH BX instruction is executed.
The BIU of 8086 contains 16 bit segment registers. What is the width of address sent out by BIU of 8086 miocroprocessor?
Loop 1 : MOV A, P1
MOV P2, A
JNB P3.3, Loop1
The program does the following
In 8051 micro controller
A. INT0 and INT1 pins are normally low
B. Timer1 Interrupt Flag is auto cleared after occurrence
C. Serial interrupt is auto cleared after occurrence
D. Timer 0 Vector location is 000B H
Choose the correct answer from the options given below:
In 8086
A. The stack memory is a FIFO (First In First Out)
B. The JMP instruction cannot be prefixed with segment override prefix
C. SAHF and POPF instructions affect the flag register
D. DAS instruction cannot be used for 8 bit operations.
Choose the correct answer from the options given below :
In 8051
A. INT0 and INT1 can be made edge triggered by programming TCON
B. On reset serial communication interrupts has highest priority
C. Upon reset all interrupts are enabled
D. Only one interrupt is set aside for serial communication.
Choose the correct answer from the options given below:
Match List I with List II in 8086 Micro processor
| LIST I | LIST II |
| A. Direct memory addressing data memory | I. MOV [SI], 2500 H |
| B. Immediate Addressing | II. PUSHF |
| C. Flag Manipulation | III. RET |
| D. Control transfer | IV. MOV BX, [2000 H] |
Choose the correct answer from the options given below:
Arrange following interrupts in order of polling (checking interrupt conditions) after every instructions.
A. Serial Interrupt
B. External 1 Interrupt
C. Timer 1 Interrupt
D. External 0 Interrupt
Choose the correct answer from the options given below :
Given below are two statements : one is labelled as Assertion A and the other is labelled as Reason R
Assertion A : Some instruction read the contents of an internal port latch instead of reading the status of an external pin.
Reason R : We must not make a distinction between reading the status of the input pin and internal latch of the output port.
In the light of the above statements, choose the most appropriate answer from the options given below :
An 8086 address bus is a/an _____ -bit bus
Program counter for any counter:
In the pin out configuration of the 8085 microprocessor, the sequential input data is represented by
Which of the following functions is not performed by a microprocessor?
Match the columns.
Pin | Description |
a. D 0-D 7 | 1. Reset Input |
b. RESET | 2. Data Lines |
c. A 0,A 1 | 3. Internal Address |