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Question

In 8051

A. INT0 and INT1 can be made edge triggered by programming TCON

B. On reset serial communication interrupts has highest priority

C. Upon reset all interrupts are enabled

D. Only one interrupt is set aside for serial communication.

Choose the correct answer from the options given below:

This question was previously asked in
UGC NET 2023 Electronic Science Question Paper (13-Dec-2023) (Shift 1)
The correct answer is

A and D only

A — "INT0 and INT1 can be made edge triggered by programming TCON." TRUE. The two low-order bits of the TCON register choose the trigger style:

\(\texttt{IT0 (TCON.0)},\ \texttt{IT1 (TCON.2)} = 1 \Rightarrow \text{falling-edge triggered}\)

with 0 giving level-triggered operation (the default after reset). Edge triggering is usually preferred because a level-triggered request must be removed by the external device before the ISR returns, or the interrupt fires again.

B — "On reset the serial interrupt has highest priority." FALSE. After reset the priority order runs top to bottom exactly as the vector table does:

External INT0 > Timer 0 > External INT1 > Timer 1 > Serial (lowest)

So the serial interrupt has the lowest default priority. It can be promoted by setting its bit in the IP (Interrupt Priority) register, which gives it high priority within a two-level scheme.

C — "Upon reset all interrupts are enabled." FALSE. Reset clears the IE register, so every interrupt is disabled. Software must first enable the individual source and then set the global enable bit EA:

\(\texttt{MOV IE,\#82H} \Rightarrow EA=1,\ ET0=1\ (\text{Timer 0 enabled})\)

D — "Only one interrupt is set aside for serial communication." TRUE. The 8051 has a single serial interrupt at vector 0023H shared by both the receive flag RI and the transmit flag TI — which is precisely why the ISR must poll the two flags to discover which event occurred, and clear the right one by hand.

Summary of the 8051's five interrupts: two external (INT0, INT1), two timer (T0, T1) and one serial — six vectors in all if reset is counted.

Hence, the correct statements are A and D only.

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