In 8051 A. INT0 and INT1 can be made edge triggered by programming TCON B. On reset serial communication interrupts has highest priority C. Upon reset all interrupts are enabled D. Only one interrupt is set aside for serial communication. Choose the correct answer from the options given below:
A and D only
A — "INT0 and INT1 can be made edge triggered by programming TCON." TRUE. The two low-order bits of the TCON register choose the trigger style:
\(\texttt{IT0 (TCON.0)},\ \texttt{IT1 (TCON.2)} = 1 \Rightarrow \text{falling-edge triggered}\)
with 0 giving level-triggered operation (the default after reset). Edge triggering is usually preferred because a level-triggered request must be removed by the external device before the ISR returns, or the interrupt fires again.
B — "On reset the serial interrupt has highest priority." FALSE. After reset the priority order runs top to bottom exactly as the vector table does:
External INT0 > Timer 0 > External INT1 > Timer 1 > Serial (lowest)
So the serial interrupt has the lowest default priority. It can be promoted by setting its bit in the IP (Interrupt Priority) register, which gives it high priority within a two-level scheme.
C — "Upon reset all interrupts are enabled." FALSE. Reset clears the IE register, so every interrupt is disabled. Software must first enable the individual source and then set the global enable bit EA:
\(\texttt{MOV IE,\#82H} \Rightarrow EA=1,\ ET0=1\ (\text{Timer 0 enabled})\)
D — "Only one interrupt is set aside for serial communication." TRUE. The 8051 has a single serial interrupt at vector 0023H shared by both the receive flag RI and the transmit flag TI — which is precisely why the ISR must poll the two flags to discover which event occurred, and clear the right one by hand.
Summary of the 8051's five interrupts: two external (INT0, INT1), two timer (T0, T1) and one serial — six vectors in all if reset is counted.
Hence, the correct statements are A and D only.
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DAA
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Loop 1 : MOV A, P1
MOV P2, A
JNB P3.3, Loop1
The program does the following
In 8051 micro controller
A. INT0 and INT1 pins are normally low
B. Timer1 Interrupt Flag is auto cleared after occurrence
C. Serial interrupt is auto cleared after occurrence
D. Timer 0 Vector location is 000B H
Choose the correct answer from the options given below:
In 8086
A. The stack memory is a FIFO (First In First Out)
B. The JMP instruction cannot be prefixed with segment override prefix
C. SAHF and POPF instructions affect the flag register
D. DAS instruction cannot be used for 8 bit operations.
Choose the correct answer from the options given below :
Match List I with List II in 8086 Micro processor
LIST I LIST II A. Direct memory addressing data memory I. MOV [SI], 2500 H B. Immediate Addressing II. PUSHF C. Flag Manipulation III. RET D. Control transfer IV. MOV BX, [2000 H] Choose the correct answer from the options given below:
Arrange following interrupts in order of polling (checking interrupt conditions) after every instructions.
A. Serial Interrupt
B. External 1 Interrupt
C. Timer 1 Interrupt
D. External 0 Interrupt
Choose the correct answer from the options given below :
Given below are two statements : one is labelled as Assertion A and the other is labelled as Reason R
Assertion A : Some instruction read the contents of an internal port latch instead of reading the status of an external pin.
Reason R : We must not make a distinction between reading the status of the input pin and internal latch of the output port.
In the light of the above statements, choose the most appropriate answer from the options given below :
The ALE line of an 8085 microprocessor is used to
Important Questions from Microprocessors
An 8086 address bus is a/an _____ -bit bus
Program counter for any counter:
In the pin out configuration of the 8085 microprocessor, the sequential input data is represented by
Which of the following functions is not performed by a microprocessor?
Match the columns.
Pin
Description
a. D 0-D 7
1. Reset Input
b. RESET
2. Data Lines
c. A 0,A 1
3. Internal Address
