In 8051 micro controller A. INT0 and INT1 pins are normally low B. Timer1 Interrupt Flag is auto cleared after occurrence C. Serial interrupt is auto cleared after occurrence D. Timer 0 Vector location is 000B H Choose the correct answer from the options given below:
B and D only
To determine the correct answer, let's analyze each of the statements provided in the question about the 8051 microcontroller:
- Statement A: INT0 and INT1 pins are normally low
- This statement is not correct. Typically, the INT0 and INT1 external interrupt pins can be configured to be either level-triggered or edge-triggered. In the case of level-triggered, they can be high-level or low-level. Therefore, this statement is not universally true without specific configuration.
- Statement B: Timer1 Interrupt Flag is auto cleared after occurrence
- This statement is correct. In the 8051 microcontroller, the Timer interrupt flags in the TCON (Timer Control) register are automatically cleared by the hardware after the CPU acknowledges the interrupt.
- Statement C: Serial interrupt is auto cleared after occurrence
- This statement is not correct. The Serial interrupt flags (TI and RI) in the SCON (Serial Control) register are not automatically cleared by hardware. They must be cleared by software after the interrupt is processed.
- Statement D: Timer 0 Vector location is 000B H
- This statement is correct. The interrupt vector location for the Timer 0 Overflow Interrupt in the 8051 microcontroller is 000B H.
Now, based on the analysis:
- Statement B is correct because Timer1's interrupt flag is automatically cleared by the hardware.
- Statement D is correct because Timer 0's vector location is indeed 000B H.
- Therefore, the correct answer is B and D only.
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