Consider the following circuit, the switch S1 allows the output to switch between two ranges of amplitudes from 0-0.1 V and 0-1 V. Arrange these values of R1, R2 and R3 in increasing order. (A) Value of R1 Choose the most appropriate answer from the options given below :
(B) Value of R2
(C) Value of R3
(C), (A), (B)
The two ranges differ by a factor of ten, and that factor is what fixes the relative sizes of the three resistors: R3 smallest, then R1, then R2 — option 1.
What the switch does. R1 and R2 are in the series path and R3 shunts the input node to ground, so the network is a potential divider whose attenuation the switch changes:
Switch closed, shorting out R2:
\(\dfrac{v_{+}}{v_{i}}=\dfrac{R_{3}}{R_{1}+R_{3}}\)
Switch open, R2 in circuit:
\(\dfrac{v_{+}}{v_{i}}=\dfrac{R_{3}}{R_{1}+R_{2}+R_{3}}\)
Why R3 must be the smallest. Both ranges attenuate the input, so the shunt arm must be small compared with the series arms — otherwise the divider would pass nearly the whole input and no range change would be possible. A shunt resistor comparable with the series resistors would give an attenuation near \(1/2\) rather than the small fractions the two ranges require.
Why R2 must be the largest. Inserting R2 must change the attenuation by the full factor of ten between the ranges, so it has to dominate the series path when it is switched in. Taking the ratio of the two divider expressions:
\(\dfrac{R_{1}+R_{2}+R_{3}}{R_{1}+R_{3}}=10\quad\Rightarrow\quad R_{2}=9\left(R_{1}+R_{3}\right)\)
so R2 is nine times the sum of the other two — comfortably the largest of the three. R1 is therefore left in the middle, and the order is R3 < R1 < R2.
Why the divider feeds the non-inverting input. That terminal draws essentially no current, so it does not load the divider and the ratio above holds exactly. The op-amp then buffers the divided signal, presenting a low output impedance to whatever follows — which is precisely why an attenuator of this kind is built round an amplifier rather than used bare.
The design principle in one line : in a switched-range attenuator the shunt element sets the basic division and the switched series element sets the range ratio, so the shunt is always the smallest and the switched series element the largest.
Hence, the increasing order is (C), (A), (B).
Assertion (A) : An Op-Amp is a direct coupled high gain amplifier.
Reason (R) : It consists of one or more differential amplifiers and usually followed by a level translator and push pull stage.
The input to a differentiator is –5 V. Its output will be
Match the following :
| List – I | List – II |
| a. h-parameters | i. O/P voltage varies as the slope of i/p voltage |
| b. differentiator | ii. Noise division |
| c. half-wave rectifier | iii. Function of a Q point |
| d. integrator | iv. series diode clipper |
Codes :
Assertion (A) : Op-Amp is used for sensor circuit.
Reason (R) : A small signal amplifier amplify weak measured signals.
The given operational amplifier circuit corresponds to which electronic circuit application ?

Statements in connection to Op-Amp applications are :
A. If we use a square wave generator followed by integrator circuit we get a triangular wave at the output
B. The logarithmic amplifier called a log-amplifier or a logger, is basically a current to voltage converter.
C.
is a first order high pass filter with voltage follower
D. If we use a square wave generator followed by a clipping circuit then we get a saw-tooth wave generator.
Choose the correct answer from the options given below:
Match List I with List II
| LIST I | LIST II | ||
|---|---|---|---|
| A. | Single polarity positive voltage clipper circuit | I. | ![]() |
| B. | Negative clamping circuit | II. | ![]() |
| C. | Differentiator circuit | III. | ![]() |
| D. | Logarithmic Amplifier | IV. | ![]() |
Choose the correct answer from the options given below:
The correct flow in the basic block diagram of op-Amp is
A. Complementary symmetry push pull amplifier block.
B. Dual input unbalanced output differential amplifier block
C. Emitter follower with constant current source block
D. Dual-Input balanced output differential amplifier block
Choose the correct answer from the options given below :
Match the following :
| List - I | List - II |
a) ![]() | i) ![]() |
b) ![]() | ii) ![]() |
c) ![]() | iii) ![]() |
d) ![]() | iv) ![]() |
Codes :
\(\dfrac{d^{2}y}{dt^{2}}+y=0\) can be solved using an Operational Amplifier. Which one is preferred ?
In the circuit shown below, $R$ is $1\text{ k}\Omega$ and $R_f$ is $10\text{ k}\Omega$. If $V_{\text{in}}$ is $100\text{ mV}$ and the op-amps have supply voltages of $\pm 15\text{ V}$, then $V_{\text{out}}$ is _______ V.

For IC 741 circuit shown below, the maximum input frequency above which the output will be distorted is ____________.

Assume that an op-amp 741 connected as a unit gain inverting amplifier is applied with an input change of 10 V. Determine the time taken for the output to change by 10 V. [Slew rate for op-amp 741 = 0.5 V/µs]
What is the value of output voltage $V_o$ in the given circuit? Assume op-amp to be ideal and MOSFET operating in saturation region.
In an ideal op-amp, the common mode gain is _____________.