The number of flip-flops required to design a modulo - 272 counter is :
9
A modulo-N counter needs the smallest number of flip-flops n such that \(2^{n} \geq N\), because n flip-flops give \(2^{n}\) distinct states.
\(2^{8} = 256 \lt 272\)
\(2^{9} = 512 \geq 272\)
So 8 flip-flops are too few, while 27 or 11 flip-flops would work but are more than the minimum.
Check: \(\lceil \log_{2} 272 \rceil = \lceil 8.09 \rceil = 9\).
Hence, 9.
Similar Questions
Consider a 3-bit counter, designed using T flip flops as shown below:
Assume the initial state of the counter given by PQR as 000, what are the next three states?
Match List - I with List - II.
List - I (Counter) List - II (uses/working) (A) N-bit Ring Counter (I) Uses universal clock (B) Synchronous Counter (II) Counts exactly N states (C) Asynchronous Counter (III) Counts 0 to 9 (D) Decimal Counter (IV) Main clock is applied to first flip-flop only Choose the correct answer from the options given below :
A binary 3-bit down counter uses J-K flip-flops, FFi with inputs Ji, Ki and outputs Qi, i = 0, 1, 2 respectively. The minimized expression for the input from following, is
I. J0 = K0 = 0
II. J0 = K0 = 1
III. J1 = K1 = Q0
IV. J1 = K1 = \(\overline{Q_0}\)
V. J2 = K2 = Q1 Q0
VI. J2 = K2 = \(\overline{Q_1}\,\overline{Q_0}\)
Important Questions from Counter
Which is not related to the counter circuit design?
A 16-bit synchronous binary up-counter is clocked with a frequency fCLK. The two most significant bits are OR-ed together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is 24 ms. The clock frequency fCLK is ______ MHz. (Round off 2 decimal places.)
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)
A modulus 10 counter must have
How many flip-flops circuits are needed for a 4 bit counter?
