A 16-bit synchronous binary up-counter is clocked with a frequency fCLK. The two most significant bits are OR-ed together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is 24 ms. The clock frequency fCLK is ______ MHz. (Round off 2 decimal places.)
Given:
Output (Y) is high (1) for the time period of 24 ms.
Q15 Q14 Q13 ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Q0
Y = 1 begins at: 0100 0000 0000 ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ 0000
Y = 1 end at: 1111 1111 1111 ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ 1111
Number of states in which Y is low (0) = 214
Total number of states = 216
Number of states in which Y is high (1) = 216 - 214
Time when Y is high (1) in 216 - 214 = 24 × 10-3 s
Total time (T) = \(24\;\times 10^{-3} \over 2^{16}\;-\;2^{14} \)
Frequency = \({1\over {T}} = {2^{16}\;-2^{14} \over {} 24\;\times\;10^{-3}} = 2.048\;MHz \)
Important Questions from Counter
Which of the following is not capable of storing binary data?
A _________ is a register capable of counting the number of clock pulses arriving at its clock input.
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)
A counter is constructed with three D flip-flops. The input-output pairs are named (D0, Q0), (D1, Q1), and (D2, Q2), where the subscript 0 denotes the least significant bit. The output sequence is desired to be the Gray-code sequence 000, 001, 011, 010, 110, 111, 101, and 100, repeating periodically. Note that the bits are listed in the Q2 Q1 Q0 format. The combinational logic expression for D1 is
A modulus 10 counter must have
