A 16-bit synchronous binary up-counter is clocked with a frequency fCLK. The two most significant bits are OR-ed together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is 24 ms. The clock frequency fCLK is ______ MHz. (Round off 2 decimal places.)
Given:
Output (Y) is high (1) for the time period of 24 ms.
Q15 Q14 Q13 ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Q0
Y = 1 begins at: 0100 0000 0000 ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ 0000
Y = 1 end at: 1111 1111 1111 ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ 1111
Number of states in which Y is low (0) = 214
Total number of states = 216
Number of states in which Y is high (1) = 216 - 214
Time when Y is high (1) in 216 - 214 = 24 × 10-3 s
Total time (T) = \(24\;\times 10^{-3} \over 2^{16}\;-\;2^{14} \)
Frequency = \({1\over {T}} = {2^{16}\;-2^{14} \over {} 24\;\times\;10^{-3}} = 2.048\;MHz \)
Important Questions from Counter
Which is not related to the counter circuit design?
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)
A modulus 10 counter must have
How many flip-flops circuits are needed for a 4 bit counter?
- In a 4-bit ripple counter, if the period of the waveform at the last flip-flop is 64 microseconds, then the frequency of the ripple counter in kHz is __________. (Answer in integer)
