Consider a 3-bit counter, designed using T flip flops as shown below: Assume the initial state of the counter given by PQR as 000, what are the next three states?
011, 101, 000
A T flip-flop toggles its output on the clock edge when T = 1 and holds it when T = 0, so Qnext = T ⊕ Q. In the circuit all three flip-flops share the clock, and the wiring read from the diagram is Tp = R (feedback from the last stage), Tq = P’ and Tr = Q’.
Step 1 — Simulate each clock edge from PQR = 000:
| Present PQR | Tp = R | Tq = P’ | Tr = Q’ | Next PQR |
|---|---|---|---|---|
| 000 | 0 | 1 | 1 | 011 |
| 011 | 1 | 1 | 0 | 101 |
| 101 | 1 | 0 | 1 | 000 |
Step 2 — From 000: P holds (Tp = 0), Q and R toggle, giving 011. From 011: P and Q toggle, R holds, giving 101. From 101: P and R toggle, Q holds, giving 000. The counter returns to its initial state after three clocks.
The sequences 001, 010, 111 and 001, 010, 000 are binary up-count patterns that ignore the feedback wiring, and 011, 101, 111 gets the third state wrong because with Tq = P’ = 0 at state 101 the Q output cannot toggle to 1.
011, 101, 000 option is correct.
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III. J1 = K1 = Q0
IV. J1 = K1 = \(\overline{Q_0}\)
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