Match List - I with List - II. Choose the correct answer from the options given below :List - I (Counter) List - II (uses/working) (A) N-bit Ring Counter (I) Uses universal clock (B) Synchronous Counter (II) Counts exactly N states (C) Asynchronous Counter (III) Counts 0 to 9 (D) Decimal Counter (IV) Main clock is applied to first flip-flop only
(A)-(II), (B)-(I), (C)-(IV), (D)-(III)
Counters are sequential circuits built from flip-flops; they differ in how the clock is distributed and in how many distinct states they cycle through.
(A) An N-bit ring counter is a shift register whose output feeds back to its input, circulating a single 1; with N flip-flops it has exactly N states, entry (II).
(B) A synchronous counter drives every flip-flop from the same common (universal) clock, so all of them change state together, entry (I).
(C) An asynchronous (ripple) counter applies the main clock only to the first flip-flop; each later flip-flop is clocked by the output of the previous one, entry (IV).
(D) A decimal (decade, BCD) counter has ten states and counts 0 to 9 before resetting, entry (III).
So the matching is (A)-(II), (B)-(I), (C)-(IV), (D)-(III); codes that give the common clock to the ripple counter or the first-flip-flop clock to the synchronous counter swap the defining property of the two.
(A)-(II), (B)-(I), (C)-(IV), (D)-(III) option is correct.
The number of flip-flops required to design a modulo - 272 counter is :
Consider a 3-bit counter, designed using T flip flops as shown below:

Assume the initial state of the counter given by PQR as 000, what are the next three states?
A binary 3-bit down counter uses J-K flip-flops, FFi with inputs Ji, Ki and outputs Qi, i = 0, 1, 2 respectively. The minimized expression for the input from following, is
I. J0 = K0 = 0
II. J0 = K0 = 1
III. J1 = K1 = Q0
IV. J1 = K1 = \(\overline{Q_0}\)
V. J2 = K2 = Q1 Q0
VI. J2 = K2 = \(\overline{Q_1}\,\overline{Q_0}\)
Which is not related to the counter circuit design?
A 16-bit synchronous binary up-counter is clocked with a frequency fCLK. The two most significant bits are OR-ed together to form an output Y. Measurements show that Y is periodic, and the duration for which Y remains high in each period is 24 ms. The clock frequency fCLK is ______ MHz. (Round off 2 decimal places.)
A MOD 2 and a MOD 5 up-counter when cascaded together results in a MOD ______ counter. (in integer)
A modulus 10 counter must have
How many flip-flops circuits are needed for a 4 bit counter?