8085 Bus Technique for Memory and I/O Access

The Intel 8085 microprocessor employs a specific method to handle communication pathways for both memory and I/O devices, focusing on pin efficiency.

Multiplexed Address/Data Bus Explained

The core technique used by the 8085 is the multiplexed address/data bus. This approach uses a single set of pins for transmitting both the address and the data, but sequentially.

• Initially, the 8085 outputs the memory or I/O address on the pins AD0 through AD7 (along with A8-A15 for the full 16-bit address).
• The Address Latch Enable (ALE) signal indicates that the lower 8 bits on AD0-AD7 represent the address. An external latch captures this address.
• After the ALE signal goes low, the same pins (AD0-AD7) are repurposed for data transfer (reading from or writing to the selected location/device).

This multiplexing reduces the total number of pins needed for the processor.

Analysis of Alternatives

• Separate memory and I/O buses: The 8085 uses control signals (like IO/M̅) to differentiate between memory and I/O operations, but it shares the physical address/data lines, unlike systems with truly separate buses for each.
• Harvard architecture: The 8085 follows the Von Neumann architecture, having a unified address space for both instructions and data, distinct from the Harvard architecture's separate spaces.
• Fully asynchronous bus: The 8085 bus operations are timed using specific control signals (RD̅, WR̅, ALE, etc.), making it synchronous or partially asynchronous, not fully asynchronous where transfers complete purely based on device readiness without strict timing coordination.

Consequently, the defining technique for memory and I/O access in the 8085 is its multiplexed bus structure.