For the given emitter-bias network, determine the values of $I_C$ and $V_{CE}$. Assume $\beta = 100$.
To determine the values of \(I_C\) (collector current) and \(V_{CE}\) (collector-emitter voltage) for the given emitter-bias network, we need to follow these steps:
Given Values:
Step 1: Determine \(I_E\) (Emitter Current)
Using the approximation \(I_E \approx I_C\) (since \(\beta \approx 100\)), we find \(I_E\).
Assuming a voltage across \(R_E\) due to emitter current:
\(V_{E} = I_{E} \times R_{E}\)
Using Kirchhoff's Voltage Law (KVL) in the input loop:
\(V_{CC} = I_{E} \times R_{E} + V_{BE} + I_B \times R_1\) \(15 = I_{E} \times 1k + 0.7 + \frac{I_{E}}{\beta} \times 330k\)
Assuming \(I_B\) is much smaller than \(I_E\), the voltage drop across \(R_1\) can be small, we approximate:
\(I_E \approx \frac{14.3}{331} \approx 43.2 \, mA\)
Step 2: Relate \(I_E\) to \(I_C\)
Since \(I_C \approx \beta I_B\):
\(I_C = \frac{\beta}{\beta+1} \times I_E \approx \frac{100}{101} \times 43.2 \, mA \approx 43.1 \, mA\)
Step 3: Determine \(V_{CE}\)
Using KVL for the outer loop:
\(V_{CC} = I_C \times R_2 + V_{CE} + I_E \times R_E\)
Rearrange and solve for \(V_{CE}\):
\(15 = 43.1 \, mA \times 2k + V_{CE} + 43.2 \, mA \times 1k\) \(V_{CE} = 15 - 86.2 - 43.2 \approx 5.04 \, V\)
Conclusion
The calculated values are \(I_C \approx 43.2 \, mA\) and \(V_{CE} \approx 5.04 \, V\). Matching with the options provided, the correct answer is:
| List - I (Addressing Modes) | List - II (Instruction) |
| A. Immediate Addressing | I. LDAX B |
| B. Register Addressing | II. OUT 01H |
| C. Direct Addressing | III. MVI B, 37H |
| D. Indirect Addressing | IV. MOV A, B |
| List - I | List - II |
| (Memory) | (Characteristic) |
| A. ROM | I. Volatile, Fast, Expensive |
| B. EPROM | II. UV erasable |
| C. EEPROM | III. Electrically erasable |
| D. SRAM | IV. Non-Volatile, permanent data |
| List - I | List - II |
| (Bus/Logic) | (Function/Characteristic) |
| A. Address bus | I. Carries read/write signals, timing signals, and interrupt signals |
| B. Data bus | II. A three-state output that can be high, low, or high-impedance |
| C. Control bus | III. Unidirectional lines used by CPU to point to a memory location or I/O device |
| D. Tristate logic | IV. Bidirectional lines used for transferring data between the CPU and memory |