A Phase-Locked Loop (PLL) is a feedback control system that forces a locally generated signal to track the frequency and phase of an incoming reference signal. It has three core blocks connected in a loop: a phase detector (PD), a low-pass filter (LPF), and a voltage-controlled oscillator (VCO) whose output is fed back to the detector.

The job of the phase detector is to compare the instantaneous phase of the input signal with the phase of the VCO feedback signal and produce an output that depends on the difference between them. For an ideal detector this output is:

• Proportional to the phase error (Δφ) between the two inputs — a small misalignment gives a small correcting voltage, a large misalignment gives a large one.
• This error voltage is smoothed by the LPF and applied as the control voltage of the VCO, nudging the VCO frequency in the direction that shrinks the phase difference until the loop settles.

This is exactly why the correct description is a proportional error voltage produced when the detector sees a phase difference between the input and the VCO signal — that proportionality is the very mechanism the loop uses to correct itself.

Why the other descriptions are wrong:

• The claim that the output is zero when the phases are perfectly aligned describes only one special operating point (the locked, zero-error condition), not the general behaviour of the detector, which is defined by how it responds to a phase difference.
• A maximum constant voltage in the free-running state is incorrect: when free-running (no valid lock), the VCO runs at its natural frequency and the detector output is a time-varying beat signal, not a fixed maximum DC level.
• An alternating current signal when the loop is locked is the opposite of reality — once locked, the phase difference is steady, so the useful detector output is a constant DC (error) level, not an AC waveform.