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Following multiplexers have to be designed by different MUX. Arrange the number of MUX required in descending order

A. Construct 4 : 1 MUX by using 2 : 1 MUX

B. Construct 16 : 1 MUX by using 4 : 1 MUX

C. Construct 64 : 1 MUX by using 4 : 1 MUX

D. Construct 64 : 1 MUX by using 8 : 1 MUX

E. Construct 256 : 1 MUX by using 8 : 1 MUX

Choose the correct answer from the options given below :

This question was previously asked in
UGC NET 2023 Paper 1 Question Paper (22-Jun-2023) (Shift 2)
The correct answer is

\(E \gt C \gt D \gt B \gt A\)

How a large MUX is built from smaller ones. The small multiplexers are arranged as a tree. Each level reduces the number of lines by the factor of the building block, and the process repeats until a single output remains. For an N:1 MUX built from k:1 blocks the levels hold N/k, N/k², N/k³ … units, so the total is

\(\text{Total}=\dfrac{N}{k}+\dfrac{N}{k^{2}}+\ldots+1\)

Count each case.

ItemRequirementLevelsTotal MUXes
4:1 from 2:12 + 13
B16:1 from 4:14 + 15
C64:1 from 4:116 + 4 + 121
D64:1 from 8:18 + 19
E256:1 from 8:132 + 4 + 137

Worked illustration (case C). Sixteen 4:1 MUXes in the first level cover all 64 inputs and reduce them to 16 lines; four more reduce those to 4; one final MUX gives the single output — 16 + 4 + 1 = 21, using three levels of select decoding (2 bits per level, 6 select bits in all, as required for 64 inputs).

Arrange in descending order: 37 (E) > 21 (C) > 9 (D) > 5 (B) > 3 (A), i.e.

\(E \gt C \gt D \gt B \gt A\)

Design insight. Compare C and D — the same 64:1 function costs 21 blocks with 4:1 units but only 9 with 8:1 units. Larger building blocks mean fewer levels, hence fewer devices and less propagation delay, since delay scales with the number of levels, \(\log_k N\).

Hence, the descending order is E > C > D > B > A.

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Similar Questions

  1. Consider the following statements :

    A multiplexer :

    1. selects one of the several inputs and transmits it to a single output.
    2. routes the data from a single input to one of many outputs.
    3. converts parallel data into serial data.
    4. is a combinational circuit.

    Which of these statements are correct ?

  2. Consider the following statements :

    (A) An 8-input MUX can be implemented using any 4 variable function
    (B) A 3-line to 8-line DEMUX can be used to implement any 4 variable functions
    (C) A 64-input MUX can be built using nine 8-input MUXs
    (D) A 6-line to 64-line DEMUX can be built using nine 3-line DEMUXs

    Choose the most appropriate answer from the options given below :

  3. For the given 4 × 1 MUX, the output y is


Important Questions from Multiplexer

  1. The number of control lines in a multiplexer is 5, identify the MUX.

  2. Number of control lines required for 16 to 1 multiplexer is _____

  3. In a multiplexer, the number of input lines is ‘n’ and the number of select lines is ‘m’. Which of the following is correct?

  4. ________ is used to carry digital data on analog lines.

  5. Consider a logic gate circuit. with 8 input lines (D 0, D 1..... D 7) and 3 output lines (A 0, A 1, A 2) specified by following operations

    A 2= D 4+ D 5+ D 6+ D 7

    A 1= D 2+ D 3+ D 6+ D 7

    A 0= D 1+ D 3+ D 5+ D 0

    Where + indicates logical OR operation. This circuit is

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