Statement 2 describes a demultiplexer, not a multiplexer, so the correct set is 1, 3 and 4 — option 3.

Statement 1 — the definition. A \(2^{n}\)-to-1 multiplexer has \(2^{n}\) data inputs, n select lines and one output; the select code names which input reaches the output. For a 4-to-1:

\(Y=\overline{S_{1}}\,\overline{S_{0}}I_{0}+\overline{S_{1}}S_{0}I_{1}+S_{1}\overline{S_{0}}I_{2}+S_{1}S_{0}I_{3}\)

Statement 3 follows from statement 1. Drive the select lines from a binary counter and the inputs are visited one after another, so a word presented in parallel emerges as a serial stream on the single output line — parallel-to-serial conversion using nothing but a MUX and a counter. The demultiplexer at the far end, driven by a matching counter, reverses it. This is exactly how time-division multiplexing works.

Statement 4 — combinational. The output depends only on the present inputs and select code. There is no feedback path and no memory element, so the same inputs always give the same output, with no dependence on what came before. A multiplexer used inside a sequential circuit — as the input selector of a loadable flip-flop, for instance — does not make the multiplexer itself sequential.

One further use worth noting : because the expression above is a full sum of minterms, a \(2^{n}\)-to-1 multiplexer can implement any n-variable Boolean function directly — wire the variables to the select lines and the truth-table values to the data inputs. With the Shannon expansion, a function of n+1 variables can even be realised on a \(2^{n}\)-to-1 device. This makes the multiplexer a universal logic element, which is why FPGA logic blocks are built largely from them.

Hence, statements 1, 3 and 4 are correct.