A digital computer has a common bus system for 8 registers 16 bits each. How many multiplexers are required to implement common bus? What size of multiplexers is required?
16, 8 × 1
A common bus system in a digital computer is a set of shared lines used to transfer data between different components like registers, memory, and the CPU. Instead of having separate connections between every pair of components, a bus allows multiple devices to share a single set of wires. To control which device is putting data onto the bus at any given time, and which device is receiving data, control signals and logic gates like multiplexers and decoders are used.
In this question, we are looking at implementing a common bus for 8 registers, each capable of storing 16 bits of data. This means each register has 16 individual storage elements (like flip-flops), one for each bit position.
To allow any one of the 8 registers to place its 16-bit value onto a common bus, we need a mechanism to select one out of the eight 16-bit inputs at any time. Multiplexers are ideal for this purpose. A multiplexer is a data selector; it takes multiple input lines and routes one of them to a single output line, based on the state of its select lines.
The registers are 16 bits wide. This means there are 16 parallel lines in the common bus, one for each bit position (bit 0, bit 1, ..., bit 15). For the bus line corresponding to bit position 'i' (e.g., bit 0), we need to be able to select the bit 'i' value from any of the 8 registers. This selection process happens independently for each bit position.
Since this selection process must occur for each of the 16 bits simultaneously, we need one multiplexer for each bit position.
Therefore, the total number of multiplexers required is equal to the number of bits in each register.
Number of multiplexers = Number of bits per register = 16.
The size of a multiplexer is determined by the number of input lines it can select from. In this common bus system, for any given bit position, the multiplexer needs to select the data from the corresponding bit of one of the 8 registers.
There are 8 such input lines for each multiplexer. A multiplexer with 8 input lines and 1 output line is called an 8-to-1 multiplexer. The 'size' is typically described as the number of inputs 'times' the number of outputs (which is usually 1 for a standard multiplexer). So, the size is 8 $\times$ 1.
Size of multiplexer = Number of registers $\times$ 1 = 8 $\times$ 1.
Based on the analysis:
So, we need 16 multiplexers of size 8 $\times$ 1.
| Component | Value/Requirement |
|---|---|
| Number of Registers | 8 |
| Bits per Register | 16 |
| Common Bus Width | 16 bits |
| Multiplexers Needed | 16 (one per bit line) |
| Inputs per Multiplexer | 8 (one from each register) |
| Size of Multiplexer | 8 $\times$ 1 |
Comparing this with the given options, the requirements are 16 multiplexers, each of size 8 $\times$ 1.
| Concept | Explanation |
|---|---|
| Common Bus | Shared set of wires for data transfer between multiple components. |
| Multiplexer (MUX) | A digital circuit that selects one of several input signals and forwards the selected input into a single output line. Acts as a data selector. |
| Number of MUXes in Bus | Typically equals the width of the bus (number of bits). |
| Size of MUX (N $\times$ 1) | N is the number of sources (components) that can drive the bus. |
Implementing a common bus system also requires control logic. While multiplexers select the source register, control signals are needed to determine which register's data is selected by the multiplexers and which register (or other component) will receive the data from the bus (destination). Decoders are often used to enable the correct register to load data from the bus. For an 8-register system, 3 select lines are needed for the 8 $\times$ 1 multiplexers ($2^3 = 8$). These select lines are part of the bus control unit.
Furthermore, registers typically have load enable inputs. A decoder could be used to activate the load enable of the desired destination register based on the destination address specified by the control unit.
The device which changes from serial data to parallel data is:
Consider a logic gate circuit. with 8 input lines (D 0, D 1..... D 7) and 3 output lines (A 0, A 1, A 2) specified by following operations
A 2= D 4+ D 5+ D 6+ D 7
A 1= D 2+ D 3+ D 6+ D 7
A 0= D 1+ D 3+ D 5+ D 0
Where + indicates logical OR operation. This circuit is
Which of the following statements are true?
A. Frequency division multiplexing technique can be handled by digital circuits.
B. Time division multiplexing technique can be handled by analog circuits
C. Wavelength division multiplexing technique is used with optical fiber for combining two signals.
D. Frequency division multiplexing technique can be applied when the bandwidth of a link is greater than the bandwidth of the signals to be transmitted.
Choose the correct answer from the options given below :
Consider the sentence below.
There is a country that borders both India and Pakistan.
Which of the following logical expressions express the above sentence correctly when the predicate Country(x) represents that x is a country and Borders(x, y) represents that the countries x and y share the border?
In a multiplexer, the number of input lines is ‘n’ and the number of select lines is ‘m’. Which of the following is correct?